[PATCH v4] SDRAM Calibration Failed fix for GEN5 SoCFPGA

[Sune Brian]

Hi Ralph,

On Wed, Dec 17, 2025 at 4:18 AM Ralph Siemsen <ralph.siemsen at linaro.org> wrote:
>
> On Thu, Dec 11, 2025 at 2:15 PM Sune Brian <briansune at gmail.com> wrote:
> >
> > > > Issue 2:
> > > > For DRAM size larger than 1GB, when w/o O.C. and using as stable
> > > > setting as possible.
> > > > Even it passed the calibration it will not cont'd boot when
> > > > sdram_gen5.c is turned on debug flag via "#define LOG_DEBUG"
> > > > However this issue is not found on 1GB nor 512MB.
> > >
> > > I was able to get access to board with 2GB, and it boots successfully.
> > > Memory calibration completes, and subsequent test with u-boot "mtest"
> > > basic memory test is also passing.
> >
> > For your 2GB case it is w/o CYCLIC and WDT right?
>
> Correct. Both my 512MB and 2GB are without CYCLIC and WDT.
>
> > For this may I ask what DDR3 speed you used? 400MHz?
>
> Yes, it is 400MHz, at least on the 512MB board.

For this let me recap the situation.
1) 400MHz on any size could run w/o CYCLIC nor WDT.
Disregarded to die configuration nor die size aka page size 1k or 2k etc.
>From 512 to 2G.
2) 533MHz only properly run w/o CYCLIC nor WDT on twinDie setup
3) 500MHz is required to backoff when CYCLIC and WDT is turned off on 2k
page size die on max 2G case.

So basically speaking it is about the delay tap on the sequence.c is very
timing dependent and toucky.

>
> > For 2GB there are different die configurations 512x16 itself also come with
> > different forms. If possible can you provide the actual die part #?
>
> Unfortunately I don't have physical access (nor schematics) to check that.
>
> > The most puzzling part is this. It only dies on the U-Boot stage.
> > The ddr sequence.c was somehow cropped to a point for only size and
> > speed for the file comments.
> > All boards or cases that even by luck passed the calibration phase on U-Boot
> > do not have any issue on all stressapptest nor memtester under distro.
>
> I guess I have been lucky then. My only real problem was that
> CONFIG_TIMER_COUNTS_DOWN needs to be enabled. And it was quite an
> adventure to find that (using git bisect). There are other issues,
> such as watchdog kicking in if there are too many printfs(), and also
> early uart access is broken.
>
> Ralph

Long story short when CYCLIC/WDT is off just back off DDR speed to stable.
However it makes no sense to trade off possible system speed when it is allowed
to reach 533.333MHz.

Brian