[PATCH v4] SDRAM Calibration Failed fix for GEN5 SoCFPGA

[Sune Brian]

> > Issue 1:
> > sequencer.c if turned on debug by including this at the very top.
> > "#define LOG_DEBUG" and "#define DLEVEL 1 or 2"
> > If will stall somehow on any brand of board my side current had.
>
> I also encountered this, but it was solved by disable the watchdog, by
> toggling L4WD0 reset. After doing this, there is no problem with using
> DLEVEL 2. I even took it a step further and logged every single write
> to the DDR control registers.

Hi Ralph,

Thanks again. Quick test on your proposed method.

diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c
index 3c79bb11802..904f9bc6d03 100644
--- a/drivers/ddr/altera/sdram_gen5.c
+++ b/drivers/ddr/altera/sdram_gen5.c
@@ -589,6 +589,9 @@ static int altera_gen5_sdram_probe(struct udevice *dev)
        }
        reset_deassert_bulk(&resets);

+       socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
+       socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
+
        if (sdram_mmr_init_full(sdr_ctrl, 0xffffffff) != 0) {
                puts("SDRAM init failed.\n");
                goto failed;

Works and all debug_log and max level=2.

However the same behavior can be repeated when CYCLIC / WDT off.
It will fail and once CYCLIC is turned on it will pass again.

If HW level does not support the 533.333M timing from the beginning
it is a 100% fail and no possible turning back to work.
AKA you won't be able to do any timing shift to make it work.
The DDR3 chip dies are unchanged and twin dies can always run 533.333
and never stall on the calibration phase w/ CYCLIC.

So simply speaking the sequence.c somehow is so touchy on timing.
I do test the most common timing bin of the DDR3 die.
I guess there is no easy fix on this issue unless Altera do change a bit the
sequence.c syntax.

Brian