[PATCH v4] SDRAM Calibration Failed fix for GEN5 SoCFPGA

[Ralph Siemsen]

On Thu, Dec 11, 2025 at 2:51 PM Sune Brian <briansune at gmail.com> wrote:
> Hi Ralph,
>
> Thanks again. Quick test on your proposed method.
>
> diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c
> index 3c79bb11802..904f9bc6d03 100644
> --- a/drivers/ddr/altera/sdram_gen5.c
> +++ b/drivers/ddr/altera/sdram_gen5.c
> @@ -589,6 +589,9 @@ static int altera_gen5_sdram_probe(struct udevice *dev)
>         }
>         reset_deassert_bulk(&resets);
>
> +       socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
> +       socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
> +
>         if (sdram_mmr_init_full(sdr_ctrl, 0xffffffff) != 0) {
>                 puts("SDRAM init failed.\n");
>                 goto failed;
>
> Works and all debug_log and max level=2.

Okay, great.

> However the same behavior can be repeated when CYCLIC / WDT off.
> It will fail and once CYCLIC is turned on it will pass again.

So there would seem to be another issue related to CYCLIC, hmm...

> So simply speaking the sequence.c somehow is so touchy on timing.
> I do test the most common timing bin of the DDR3 die.
> I guess there is no easy fix on this issue unless Altera do change a bit the
> sequence.c syntax.

One other complaint about sequencer.c is its size... the compile code
takes up a major portion of the 60kB size limit for SPL.

Ralph