[PATCH v4] SDRAM Calibration Failed fix for GEN5 SoCFPGA

[Sune Brian]

Hi Ralph

On Wed, Dec 17, 2025 at 4:22 AM Ralph Siemsen <ralph.siemsen at linaro.org> wrote:
>
> On Thu, Dec 11, 2025 at 2:51 PM Sune Brian <briansune at gmail.com> wrote:
> > Hi Ralph,
> >
> > Thanks again. Quick test on your proposed method.
> >
> > diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c
> > index 3c79bb11802..904f9bc6d03 100644
> > --- a/drivers/ddr/altera/sdram_gen5.c
> > +++ b/drivers/ddr/altera/sdram_gen5.c
> > @@ -589,6 +589,9 @@ static int altera_gen5_sdram_probe(struct udevice *dev)
> >         }
> >         reset_deassert_bulk(&resets);
> >
> > +       socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
> > +       socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
> > +
> >         if (sdram_mmr_init_full(sdr_ctrl, 0xffffffff) != 0) {
> >                 puts("SDRAM init failed.\n");
> >                 goto failed;
> >
> > Works and all debug_log and max level=2.
>
> Okay, great.
>
> > However the same behavior can be repeated when CYCLIC / WDT off.
> > It will fail and once CYCLIC is turned on it will pass again.
>
> So there would seem to be another issue related to CYCLIC, hmm...
>
> > So simply speaking the sequence.c somehow is so touchy on timing.
> > I do test the most common timing bin of the DDR3 die.
> > I guess there is no easy fix on this issue unless Altera do change a bit the
> > sequence.c syntax.
>
> One other complaint about sequencer.c is its size... the compile code
> takes up a major portion of the 60kB size limit for SPL.

The major concern here as I didn't fully read that file nor understand yet.
If the write is possibly ruined the data via wrong address during delay
taps trials.

Then the system is sure to stall somehow. So if the SPL phase is not
100% reliant on OCRAM only then the chance is very high to stall.
For example it uses total memory of the SDRAM lowest part i.e.
0x0 to 0x10000 etc. even this could be corrupted during the test.
However before the sequence.c could possibly reach a good delay taps,
it had been stalled by other issues and never completed.

And the most concerns from the beginning of C5 devices are they
don't even have leveling aka official don't allow fly-by yet T-branch only.

So many DDR3 standards are cropped from the beginning and even the
timing training. (I might be wrong on software level but not hardware level).

>
> Ralph

Brian