[PATCH v1] SDRAM Calibration Failed fix for GEN5 SoCFPGA

[Sune Brian]

> Looking into socfpga_cyclone5_defconfig it seems that SPL_WATCHDOG is
> enabled but no driver is. Can you tell us which (failing) defconfig
> you're using (and if it supports multiple boards, which one) so we can
> check assumptions without going back and forth with you?

Fresh build is repeatable on that calibration failure.
I have done what I can, so if there are any issues feel free to point them out.

Brian

Logs as follow:

* WDT disable DT enable fails.

* WDT enable DT enable pass.
  Warm and cold reset pass.

U-Boot SPL 2026.01-rc3-00013-gc3a95cc3c6cd-dirty (Nov 25 2025 - 07:01:29 +0800)
l4wd0-wdt_cr: 0x00000001
l4wd1-wdt_cr: 0x00000000
l4wd0-wdt_ccvr: 0x01efd394
l4wd1-wdt_ccvr: 0x00000000
SDRAM calibration failed.
l4wd0-wdt_cr: 0x00000001
l4wd1-wdt_cr: 0x00000000
l4wd0-wdt_ccvr: 0x01a3204c
l4wd1-wdt_ccvr: 0x00000000
### ERROR ### Please RESET the board ###

U-Boot SPL 2026.01-rc3-00013-gc3a95cc3c6cd-dirty (Nov 25 2025 - 07:01:29 +0800)
l4wd0-wdt_cr: 0x00000001
l4wd1-wdt_cr: 0x00000000
l4wd0-wdt_ccvr: 0x01efd2c3
l4wd1-wdt_ccvr: 0x00000000
SDRAM calibration failed.
l4wd0-wdt_cr: 0x00000001
l4wd1-wdt_cr: 0x00000000
l4wd0-wdt_ccvr: 0x01a31e7d
l4wd1-wdt_ccvr: 0x00000000
### ERROR ### Please RESET the board ###

U-Boot SPL 2026.01-rc3-00013-gc3a95cc3c6cd-dirty (Nov 25 2025 - 07:01:29 +0800)
l4wd0-wdt_cr: 0x00000001
l4wd1-wdt_cr: 0x00000000
l4wd0-wdt_ccvr: 0x01efd2ef
l4wd1-wdt_ccvr: 0x00000000
SDRAM calibration failed.
l4wd0-wdt_cr: 0x00000001
l4wd1-wdt_cr: 0x00000000
l4wd0-wdt_ccvr: 0x01a31ef2
l4wd1-wdt_ccvr: 0x00000000
### ERROR ### Please RESET the board ###

U-Boot SPL 2026.01-rc3-00013-gc3a95cc3c6cd-dirty (Nov 25 2025 - 07:01:29 +0800)
l4wd0-wdt_cr: 0x00000001
l4wd1-wdt_cr: 0x00000000
l4wd0-wdt_ccvr: 0x01efd2ac
l4wd1-wdt_ccvr: 0x00000000
SDRAM calibration failed.
l4wd0-wdt_cr: 0x00000001
l4wd1-wdt_cr: 0x00000000
l4wd0-wdt_ccvr: 0x01a31eee
l4wd1-wdt_ccvr: 0x00000000
### ERROR ### Please RESET the board ###

U-Boot SPL 2026.01-rc3-00013-gc3a95cc3c6cd-dirty (Nov 25 2025 - 07:01:29 +0800)
l4wd0-wdt_cr: 0x00000001
l4wd1-wdt_cr: 0x00000000
l4wd0-wdt_ccvr: 0x01efd318
l4wd1-wdt_ccvr: 0x00000000
SDRAM calibration failed.
l4wd0-wdt_cr: 0x00000001
l4wd1-wdt_cr: 0x00000000
l4wd0-wdt_ccvr: 0x01a31ee0
l4wd1-wdt_ccvr: 0x00000000
### ERROR ### Please RESET the board ###

U-Boot SPL 2026.01-rc3-00013-gc3a95cc3c6cd-dirty (Nov 25 2025 - 07:08:42 +0800)
l4wd0-wdt_cr: 0x00000001
l4wd1-wdt_cr: 0x00000000
l4wd0-wdt_ccvr: 0x01efd155
l4wd1-wdt_ccvr: 0x00000000
Trying to boot from MMC1


U-Boot 2026.01-rc3-00013-gc3a95cc3c6cd-dirty (Nov 25 2025 - 07:08:42 +0800)

CPU:   Altera SoCFPGA Platform
FPGA:  Altera Cyclone V, SE/A5 or SX/C5 or ST/D5, version 0x0
BOOT:  SD/MMC Internal Transceiver (3.0V)
DRAM:  2 GiB
Core:  33 devices, 18 uclasses, devicetree: separate
WDT:   Started watchdog at ffd02000 with servicing every 1000ms (10s timeout)
MMC:   dwmmc0 at ff704000: 0
Loading Environment from MMC... Reading from MMC(0)... OK
In:    serial
Out:   serial
Err:   serial
Model: Altera SOCFPGA Cyclone V SoC Development Kit
Net:   eth0: ethernet at ff702000
Hit any key to stop autoboot: 2
U-Boot SPL 2026.01-rc3-00013-gc3a95cc3c6cd-dirty (Nov 25 2025 - 07:08:42 +0800)
l4wd0-wdt_cr: 0x00000001
l4wd1-wdt_cr: 0x00000000
l4wd0-wdt_ccvr: 0x01efd0ff
l4wd1-wdt_ccvr: 0x00000000
Trying to boot from MMC1


U-Boot 2026.01-rc3-00013-gc3a95cc3c6cd-dirty (Nov 25 2025 - 07:08:42 +0800)

CPU:   Altera SoCFPGA Platform
FPGA:  Altera Cyclone V, SE/A5 or SX/C5 or ST/D5, version 0x0
BOOT:  SD/MMC Internal Transceiver (3.0V)
DRAM:  2 GiB
Core:  33 devices, 18 uclasses, devicetree: separate
WDT:   Started watchdog at ffd02000 with servicing every 1000ms (10s timeout)
MMC:   dwmmc0 at ff704000: 0
Loading Environment from MMC... Reading from MMC(0)... OK
In:    serial
Out:   serial
Err:   serial
Model: Altera SOCFPGA Cyclone V SoC Development Kit
Net:   eth0: ethernet at ff702000
Hit any key to stop autoboot:  3