[PATCH v1] SDRAM Calibration Failed fix for GEN5 SoCFPGA

[Sune Brian]

> My hunch is that SPL_WDT is enabled (or whatever other mechanism can be
> used to start the watchdog on this architecture/vendor) and somehow the
> watchdog is started in SPL but not in proper, in which case the watchdog
> isn't pinged. It could also be a remnant from the previous boot if this
> is a warm reboot (e.g. the IC isn't entirely/correctly reset before
> booting U-Boot).

For this I also tried manually master resetting the system (push button).
Hard to succeed but if "Barry Allen" suddenly helps you then it passes.
And triggered a boot and manually entered reset on command. The
system will fail as well.

Any compiled flag change i.e. optimized with size etc will even worsen
the boot success rate. Also make me feel the more you do before cal.
the worst it gets.

For register map [1].

But I am really sorry I don't have enough knowledge to debug the root
cause of it.

[1] https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html

Brian