[PATCH v3] SDRAM Calibration Failed fix for GEN5 SoCFPGA

[Sune Brian]

> Are you even sure SPL_CYCLIC is required? Wouldn't enabling CYCLIC be
> enough?

Short test answer is no. SPL_CYCLIC must be init with default timeout #.

> Since you have not identified the root issue yet, can you please provide
> the actual defconfig used before this change so we can figure out what
> is happening, if other boards are impacted and how to fix it properly so
> this possible misconfiguration cannot happen anymore?

socfpga_cyclone5_defconfig

But my patch did not target ONE config file. Because the risk or possible
hazard could happen on other GEN5 socfpga. Need others to report btw.
b.c. it requires complete fresh build to trigger possibly.

New patch V4 had pushed. CMD CYCLIC seems like not a must.

Brian