[PATCH v4 05/10] riscv: Add support for MIPS GIC syscon on RISC-V SoCs

[Yao Zi]

On Tue, Aug 19, 2025 at 10:32:53AM +0000, Uros Stajic wrote:
> From: Chao-ying Fu <cfu at mips.com>
> 
> Add basic support for the MIPS GIC syscon used on the P8700 SoC.
> Enables access to interrupt control via device tree matching.

The commit message is wrong. You cannot enable access to interrupt
controller with stub functions.

The IPI stuff, on RISC-V, is mostly used to boot HARTs into the
next-level firmware on SMP systems. As the platform does seem to contain
multiple HARTs (as indicated by the "startharts" command), they should
be implemented correctly.

...

> diff --git a/arch/riscv/lib/mips_gic.c b/arch/riscv/lib/mips_gic.c
> new file mode 100644
> index 00000000000..7d761c58e74
> --- /dev/null
> +++ b/arch/riscv/lib/mips_gic.c

...

> +int riscv_init_ipi(void)
> +{
> +	return 0;
> +}
> +
> +int riscv_send_ipi(int hart)
> +{
> +	return 0;
> +}
> +
> +int riscv_clear_ipi(int hart)
> +{
> +	return 0;
> +}
> +
> +int riscv_get_ipi(int hart, int *pending)
> +{
> +	return 0;
> +}
> +
> +static const struct udevice_id mips_gic_ids[] = {
> +	{ .compatible = "mips,gic0", .data = RISCV_SYSCON_PLICSW },
> +	{ }
> +};
> +
> +U_BOOT_DRIVER(mips_gic) = {
> +	.name		= "mips_gic",
> +	.id		= UCLASS_SYSCON,
> +	.of_match	= mips_gic_ids,
> +	.flags		= DM_FLAG_PRE_RELOC,
> +};

Regards,
Yao Zi