[PATCH v2 1/2] phytec-imx8m boards: enable OP-TEE for KASLR

[Teresa Remmet]

Hello Yannic

Am Donnerstag, dem 14.08.2025 um 14:05 +0200 schrieb Yannic Moog:
> Enable OP-TEE config and RNG by default.
> Set OP-TEE load address to end of 1GiB RAM for phycore-imx8mp as the
> board is supported in a 1GiB RAM variant.
> For the imx8mm boards, only 2GiB versions are supported, so the
> default
> at the end of 2GiB is sufficient.

sorry for the late review.
When looking at the phycore-imx8mm_defconfig I can see that
CONFIG_IMX8M_OPTEE_LOAD_ADDR is set here to 0x7e000000. 
See commit e6e8c601ed78 ("board: phytec: migrate imx8mm boards to
standard boot")
So at the end of 1GiB likewise to phyCORE-i.MX8MP and not what your
commit message says.
For tauri the default is used (end of 2GiB).
Can you please check?

Kind Regards,
Teresa

> 
> Signed-off-by: Yannic Moog <y.moog at phytec.de>
> ---
>  configs/imx8mm-phygate-tauri-l_defconfig | 5 ++++-
>  configs/phycore-imx8mm_defconfig         | 5 ++++-
>  configs/phycore-imx8mp_defconfig         | 4 ++++
>  3 files changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/configs/imx8mm-phygate-tauri-l_defconfig
> b/configs/imx8mm-phygate-tauri-l_defconfig
> index
> 7369c0a05ac98315682127f0e96af7d36c4763d2..6dc95d6d3edbc0b4ed25a66d23f
> 1b65435e01697 100644
> --- a/configs/imx8mm-phygate-tauri-l_defconfig
> +++ b/configs/imx8mm-phygate-tauri-l_defconfig
> @@ -73,9 +73,9 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y
>  CONFIG_CLK_COMPOSITE_CCF=y
>  CONFIG_SPL_CLK_IMX8MM=y
>  CONFIG_CLK_IMX8MM=y
> +CONFIG_FSL_CAAM=y
>  CONFIG_MXC_GPIO=y
>  CONFIG_DM_I2C=y
> -CONFIG_MISC=y
>  CONFIG_I2C_EEPROM=y
>  CONFIG_SYS_I2C_EEPROM_ADDR=0x51
>  CONFIG_SUPPORT_EMMC_BOOT=y
> @@ -97,11 +97,14 @@ CONFIG_IMX8M_POWER_DOMAIN=y
>  CONFIG_DM_REGULATOR=y
>  CONFIG_DM_REGULATOR_FIXED=y
>  CONFIG_DM_REGULATOR_GPIO=y
> +CONFIG_DM_RNG=y
>  CONFIG_DM_SERIAL=y
>  CONFIG_MXC_UART=y
>  CONFIG_SYSRESET=y
>  CONFIG_SPL_SYSRESET=y
>  CONFIG_SYSRESET_PSCI=y
>  CONFIG_SYSRESET_WATCHDOG=y
> +CONFIG_TEE=y
> +CONFIG_OPTEE=y
>  CONFIG_DM_THERMAL=y
>  CONFIG_IMX_WATCHDOG=y
> diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-
> imx8mm_defconfig
> index
> 4d6bce26f07f7b90e7c3674f4b9ddcac8d775e1d..4cf4d3972567bcf77d9ee7e2fda
> 707070a778c72 100644
> --- a/configs/phycore-imx8mm_defconfig
> +++ b/configs/phycore-imx8mm_defconfig
> @@ -82,9 +82,9 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y
>  CONFIG_CLK_COMPOSITE_CCF=y
>  CONFIG_SPL_CLK_IMX8MM=y
>  CONFIG_CLK_IMX8MM=y
> +CONFIG_FSL_CAAM=y
>  CONFIG_MXC_GPIO=y
>  CONFIG_DM_I2C=y
> -CONFIG_MISC=y
>  CONFIG_I2C_EEPROM=y
>  CONFIG_SYS_I2C_EEPROM_ADDR=0x51
>  CONFIG_SUPPORT_EMMC_BOOT=y
> @@ -120,6 +120,7 @@ CONFIG_POWER_DOMAIN=y
>  CONFIG_IMX8M_POWER_DOMAIN=y
>  CONFIG_DM_REGULATOR_FIXED=y
>  CONFIG_DM_REGULATOR_GPIO=y
> +CONFIG_DM_RNG=y
>  CONFIG_DM_SERIAL=y
>  CONFIG_MXC_UART=y
>  CONFIG_SPI=y
> @@ -129,5 +130,7 @@ CONFIG_SYSRESET=y
>  CONFIG_SPL_SYSRESET=y
>  CONFIG_SYSRESET_PSCI=y
>  CONFIG_SYSRESET_WATCHDOG=y
> +CONFIG_TEE=y
> +CONFIG_OPTEE=y
>  CONFIG_DM_THERMAL=y
>  CONFIG_IMX_WATCHDOG=y
> diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-
> imx8mp_defconfig
> index
> 6bd8bcf15daa95966aa973d8a493ebc1f05b14e9..c497f0bcd9131abab0b751ec9cc
> 81194405b1f19 100644
> --- a/configs/phycore-imx8mp_defconfig
> +++ b/configs/phycore-imx8mp_defconfig
> @@ -13,6 +13,7 @@ CONFIG_ENV_SECT_SIZE=0x10000
>  CONFIG_SYS_I2C_MXC_I2C1=y
>  CONFIG_DM_GPIO=y
>  CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-phyboard-pollux-rdk"
> +CONFIG_IMX8M_OPTEE_LOAD_ADDR=0x7e000000
>  CONFIG_TARGET_PHYCORE_IMX8MP=y
>  CONFIG_OF_LIBFDT_OVERLAY=y
>  CONFIG_SYS_MONITOR_LEN=524288
> @@ -153,6 +154,7 @@ CONFIG_DM_REGULATOR=y
>  CONFIG_DM_REGULATOR_FIXED=y
>  CONFIG_DM_REGULATOR_GPIO=y
>  CONFIG_SPL_POWER_I2C=y
> +CONFIG_DM_RNG=y
>  CONFIG_DM_SERIAL=y
>  CONFIG_MXC_UART=y
>  CONFIG_SPI=y
> @@ -162,6 +164,8 @@ CONFIG_SYSRESET=y
>  CONFIG_SPL_SYSRESET=y
>  CONFIG_SYSRESET_PSCI=y
>  CONFIG_SYSRESET_WATCHDOG=y
> +CONFIG_TEE=y
> +CONFIG_OPTEE=y
>  CONFIG_DM_THERMAL=y
>  CONFIG_USB=y
>  CONFIG_DM_USB_GADGET=y
> 

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