[PATCH v2] airoha: rework RAM size handling to support multiple RAM size

[Mikhail Kshevetskiy]

On 10.09.2025 02:24, Christian Marangi wrote:
> On Wed, Sep 10, 2025 at 02:16:03AM +0300, Mikhail Kshevetskiy wrote:
>> On 10.09.2025 01:57, Christian Marangi wrote:
>>> There are multiple version of the same reference board with different
>>> RAM size and it's not enough to base the RAM size entirely from DT. To
>>> better support it use the get_ram_size way to scan for the actual RAM
>>> size of Airoha SoC and increase the size of the memory map.
>>>
>>> Also rework the memory map to account for 2 memyro map. The first one of
>> Misprint, please replace 'memyro' with 'memory'.
>>
> will fix.
>
>>> 2GB for 32bit DMA and for safe usage of U-Boot. The second one for the
>>> rest of the RAM since up to 8GB are supported.
>>>
>>> Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
>>> ---
>>> Changes v2:
>>> - Add memory map to support full 8GB
>>> - Assign 2gb to first memory map for U-Boot
>>>
>>>  arch/arm/mach-airoha/an7581/init.c | 40 +++++++++++++++++++++++++-----
>>>  1 file changed, 34 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-airoha/an7581/init.c b/arch/arm/mach-airoha/an7581/init.c
>>> index d149e0ee3c8..11992027d92 100644
>>> --- a/arch/arm/mach-airoha/an7581/init.c
>>> +++ b/arch/arm/mach-airoha/an7581/init.c
>>> @@ -2,10 +2,16 @@
>>>  
>>>  #include <fdtdec.h>
>>>  #include <init.h>
>>> +#include <linux/sizes.h>
>>>  #include <sysreset.h>
>>>  #include <asm/armv8/mmu.h>
>>> +#include <asm/global_data.h>
>>>  #include <asm/system.h>
>>>  
>>> +#define CFG_MAX_MEM_MAPPED  SZ_2G
>>> +
>>> +DECLARE_GLOBAL_DATA_PTR;
>>> +
>>>  int print_cpuinfo(void)
>>>  {
>>>  	printf("CPU:   Airoha AN7581\n");
>>> @@ -14,12 +20,28 @@ int print_cpuinfo(void)
>>>  
>>>  int dram_init(void)
>>>  {
>>> -	return fdtdec_setup_mem_size_base();
>>> +	int ret;
>>> +
>>> +	ret = fdtdec_setup_mem_size_base();
>>> +	if (ret)
>>> +		return ret;
>>> +
>>> +	gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_8G);
>> I think this will not work correctly for 2 memory regions with a gap in
>> between, see  an7581_mem_map. So I think we should use get_ram_size()
>> twice (for each of regions).
>>
> There is no gap between the 2 region. I have the memory map for the SoC,
> it's from 0x80000000 to 0x280000000
>
> With specified
> 0x080000000 0x100000000 32 bit
> 0x100000000 0x280000000 64 bit

Sorry, I am not calculate it properly.

>
>>> +
>>> +	return 0;
>>>  }
>>>  
>>>  int dram_init_banksize(void)
>>>  {
>>> -	return fdtdec_setup_memory_banksize();
>>> +	gd->bd->bi_dram[0].start = gd->ram_base;
>>> +	gd->bd->bi_dram[0].size = get_effective_memsize();
>>> +
>>> +	if (gd->ram_size > SZ_2G) {
>>> +		gd->bd->bi_dram[1].start = gd->ram_base + SZ_2G;
>> gd->bd->bi_dram[1].start does not match to the virtual address of second
>> region, see  an7581_mem_map. I think this is a mistake.
> Assuming ram_base ios 0x80000000 + SZ_2G we should be at 0x100000000.
>
> Am I wrong?
I was wrong, sorry.
>>> +		gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;
>>> +	}
>>> +
>>> +	return 0;
>>>  }
>>>  
>>>  void reset_cpu(void)
>>> @@ -29,20 +51,26 @@ void reset_cpu(void)
>>>  
>>>  static struct mm_region an7581_mem_map[] = {
>>>  	{
>>> -		/* DDR */
>>> +		/* DDR, 32-bit area */
>>>  		.virt = 0x80000000UL,
>>>  		.phys = 0x80000000UL,
>>> -		.size = 0x80000000UL,
>>> +		.size = SZ_2G,
>>> +		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
>>> +	}, {
>>> +		/* DDR, 64-bit area */
>>> +		.virt = 0x100000000UL,
>>> +		.phys = 0x100000000UL,
>>> +		.size = SZ_4G + SZ_2G,
>>>  		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
>>>  	}, {
>>>  		.virt = 0x00000000UL,
>>>  		.phys = 0x00000000UL,
>>> -		.size = 0x20000000UL,
>>> +		.size = 0x40000000UL,
>>>  		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
>>>  			 PTE_BLOCK_NON_SHARE |
>>>  			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
>>>  	}, {
>>> -		0,
>>> +		/* List terminator */
>>>  	}
>>>  };
>>>  struct mm_region *mem_map = an7581_mem_map;