[PATCH v1 1/1] sunxi: extend R528/T113-s3/D1(s) DRAM initialisation

[Andre Przywara]

On Tue, 16 Sep 2025 15:35:42 +0200
András Szemző <szemzo.andras at gmail.com> wrote:

Hi András,

many thanks for the reply!

> > On 2025. Sep 15., at 17:36, Andre Przywara <andre.przywara at arm.com> wrote:
> > 
> > On Sun, 14 Sep 2025 16:44:11 +0200
> > Lukas Schmid <lukas.schmid at netcube.li> wrote:
> > 
> > Hi Lukas,
> > 
> > thanks for the patch!
> > 
> > CC:ing the sunxi list and András, who I think has some T113-s4 device as
> > well.
> >   
> 
> Thanks, but unfortunately I don’t have a board with T113-S4. 
> So awboot was not tested with this SoC, at least by me.

Ah, I see, thanks for the confirmation anyway!
I guess we will stick to the chip ID we have seen for now, and wait till
people complain.

Thanks,
Andre

> > It would be good to see some Tested-by: tags, but otherwise the patch
> > looks good, I'd say.
> > 
> > Also I hear that awboot uses 0x6800 as the chip ID for the -s4, can
> > someone shed some light on this?
> > 
> > Cheers,
> > Andre
> >   
> >> Extend the DRAM initialisation code to add support for the T113-S4 aka
> >> T113M4020DC0 by checking the SoC's CHIPID.
> >> 
> >> Signed-off-by: Lukas Schmid <lukas.schmid at netcube.li>
> >> ---
> >> drivers/ram/sunxi/dram_sun20i_d1.c | 13 ++++++++++++-
> >> drivers/ram/sunxi/dram_sun20i_d1.h |  7 +++++++
> >> 2 files changed, 19 insertions(+), 1 deletion(-)
> >> 
> >> diff --git a/drivers/ram/sunxi/dram_sun20i_d1.c b/drivers/ram/sunxi/dram_sun20i_d1.c
> >> index a1794032f3b..01d19d5feaa 100644
> >> --- a/drivers/ram/sunxi/dram_sun20i_d1.c
> >> +++ b/drivers/ram/sunxi/dram_sun20i_d1.c
> >> @@ -54,6 +54,11 @@ static void sid_read_ldoB_cal(const dram_para_t *para)
> >> clrsetbits_le32(0x3000150, 0xff00, reg << 8);
> >> }
> >> 
> >> +static u32 sid_read_soc_chipid(void)
> >> +{
> >> + return readl(SUNXI_SID_BASE + 0x00) & 0xffff;
> >> +}
> >> +
> >> static void dram_voltage_set(const dram_para_t *para)
> >> {
> >> int vol;
> >> @@ -663,6 +668,7 @@ static void mctl_phy_ac_remapping(const dram_para_t *para,
> >> 
> >> fuse = (readl(SUNXI_SID_BASE + 0x28) & 0xf00) >> 8;
> >> debug("DDR efuse: 0x%x\n", fuse);
> >> + debug("SoC Chip ID: 0x%08x\n", sid_read_soc_chipid());
> >> 
> >> if (para->dram_type == SUNXI_DRAM_TYPE_DDR2) {
> >> if (fuse == 15)
> >> @@ -675,7 +681,12 @@ static void mctl_phy_ac_remapping(const dram_para_t *para,
> >> switch (fuse) {
> >> case 8: cfg = ac_remapping_tables[2]; break;
> >> case 9: cfg = ac_remapping_tables[3]; break;
> >> - case 10: cfg = ac_remapping_tables[5]; break;
> >> + case 10:
> >> + if (sid_read_soc_chipid() == SUNXI_CHIPID_T113M4020DC0)
> >> + cfg = ac_remapping_tables[0];
> >> + else
> >> + cfg = ac_remapping_tables[5];
> >> + break;
> >> case 11: cfg = ac_remapping_tables[4]; break;
> >> default:
> >> case 12: cfg = ac_remapping_tables[1]; break;
> >> diff --git a/drivers/ram/sunxi/dram_sun20i_d1.h b/drivers/ram/sunxi/dram_sun20i_d1.h
> >> index 91383f6cf10..7bd8f67a77a 100644
> >> --- a/drivers/ram/sunxi/dram_sun20i_d1.h
> >> +++ b/drivers/ram/sunxi/dram_sun20i_d1.h
> >> @@ -19,6 +19,13 @@ enum sunxi_dram_type {
> >> SUNXI_DRAM_TYPE_LPDDR3 = 7,
> >> };
> >> 
> >> +enum sunxi_soc_chipid {
> >> + SUNXI_CHIPID_F133A = 0x5C00,
> >> + SUNXI_CHIPID_D1S = 0x5E00,
> >> + SUNXI_CHIPID_T113S3 = 0x6000,
> >> + SUNXI_CHIPID_T113M4020DC0 = 0x7200,
> >> +};
> >> +
> >> /*
> >>  * This structure contains a mixture of fixed configuration settings,
> >>  * variables that are used at runtime to communicate settings between  
> >   
>