[PATCH] arm64: zynqmp: Fix DTOVL warning about graphs in kv/kr260

[Michal Simek]

On 9/22/25 10:28, Michal Simek wrote:
> DTC is generating warnings about missing port like:
> DTOVL   arch/arm/dts/zynqmp-smk-k24-revA-sck-kv-g-revB.dtb
>   arch/arm/dts/zynqmp-sck-kv-g-revA.dtbo: Warning (graph_port):
>   /fragment at 5/__overlay__: graph port node name should be 'port'
> ...
> 
> That's why change description and add it directly to dpsub mode to contain
> full description with also port.
> 
> Signed-off-by: Michal Simek <michal.simek at amd.com>
> ---
> 
>   arch/arm/dts/zynqmp-sck-kr-g-revA.dtso | 10 ++++++----
>   arch/arm/dts/zynqmp-sck-kr-g-revB.dtso | 10 ++++++----
>   arch/arm/dts/zynqmp-sck-kv-g-revA.dtso | 12 +++++++-----
>   arch/arm/dts/zynqmp-sck-kv-g-revB.dtso | 12 +++++++-----
>   4 files changed, 26 insertions(+), 18 deletions(-)
> 
> diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
> index b92dcb86e87e..88396d089f43 100644
> --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
> +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
> @@ -154,11 +154,13 @@
>   	phy-names = "dp-phy0";
>   	phys = <&psgtr 1 PHY_TYPE_DP 0 1>;
>   	assigned-clock-rates = <27000000>, <25000000>, <300000000>;
> -};
>   
> -&out_dp {
> -	dpsub_dp_out: endpoint {
> -		remote-endpoint = <&dpcon_in>;
> +	ports {
> +		out_dp: port at 5 {
> +			dpsub_dp_out: endpoint {
> +				remote-endpoint = <&dpcon_in>;
> +			};
> +		};
>   	};
>   };
>   
> diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
> index 99ad220d13d6..e041a962d89e 100644
> --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
> +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
> @@ -155,11 +155,13 @@
>   	phy-names = "dp-phy0";
>   	phys = <&psgtr 1 PHY_TYPE_DP 0 1>;
>   	assigned-clock-rates = <27000000>, <25000000>, <300000000>;
> -};
>   
> -&out_dp {
> -	dpsub_dp_out: endpoint {
> -		remote-endpoint = <&dpcon_in>;
> +	ports {
> +		out_dp: port at 5 {
> +			dpsub_dp_out: endpoint {
> +				remote-endpoint = <&dpcon_in>;
> +			};
> +		};
>   	};
>   };
>   
> diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso
> index d7351a17d3e8..fbbebbea80cb 100644
> --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso
> +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso
> @@ -3,7 +3,7 @@
>    * dts file for KV260 revA Carrier Card
>    *
>    * (C) Copyright 2020 - 2022, Xilinx, Inc.
> - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
> + * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc.
>    *
>    * SD level shifter:
>    * "A" - A01 board un-modified (NXP)
> @@ -131,11 +131,13 @@
>   	phy-names = "dp-phy0", "dp-phy1";
>   	phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
>   	assigned-clock-rates = <27000000>, <25000000>, <300000000>;
> -};
>   
> -&out_dp {
> -	dpsub_dp_out: endpoint {
> -		remote-endpoint = <&dpcon_in>;
> +	ports {
> +		out_dp: port at 5 {
> +			dpsub_dp_out: endpoint {
> +				remote-endpoint = <&dpcon_in>;
> +			};
> +		};
>   	};
>   };
>   
> diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso
> index a4ae37ebaccf..87f94f8ef9d8 100644
> --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso
> +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso
> @@ -3,7 +3,7 @@
>    * dts file for KV260 revA Carrier Card
>    *
>    * (C) Copyright 2020 - 2022, Xilinx, Inc.
> - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
> + * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc.
>    *
>    * Michal Simek <michal.simek at amd.com>
>    */
> @@ -116,11 +116,13 @@
>   	phy-names = "dp-phy0", "dp-phy1";
>   	phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
>   	assigned-clock-rates = <27000000>, <25000000>, <300000000>;
> -};
>   
> -&out_dp {
> -	dpsub_dp_out: endpoint {
> -		remote-endpoint = <&dpcon_in>;
> +	ports {
> +		out_dp: port at 5 {
> +			dpsub_dp_out: endpoint {
> +				remote-endpoint = <&dpcon_in>;
> +			};
> +		};
>   	};
>   };
>   

Applied.
M