[PATCH 2/9] arm: hpe: Add GSC SoC support

[Jorge Cisneros]

Add core SoC support for the HPE GSC (Gen Server Controller), an ARM64
BMC SoC used in HPE Gen12 ProLiant and Synergy servers.

This includes:
- Kconfig entries for SOC_GSC with ARM64, I3C hub DT fixup, and VPD
  patching options (SYS_SOC set to "gsc")
- SoC reset implementation via writel to GSC system control register
- Architecture-level clock header for MACB Ethernet driver compatibility

The GSC reuses several GXP IP blocks (timer, SPI, I2C) while adding
new peripherals including a GICv3 interrupt controller, Cadence MACB
GEM Ethernet, and a Denali DDR memory controller.

Signed-off-by: Jorge Cisneros <jorge.cisneros at hpe.com>
---
 arch/arm/include/asm/arch-gsc/clk.h | 14 ++++++++++++++
 arch/arm/mach-hpe/gsc/reset.c       | 19 +++++++++++++++++++
 2 files changed, 33 insertions(+)

diff --git a/arch/arm/include/asm/arch-gsc/clk.h b/arch/arm/include/asm/arch-gsc/clk.h
new file mode 100644
index 00000000000..19922c433d4
--- /dev/null
+++ b/arch/arm/include/asm/arch-gsc/clk.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * HPE GSC SoC clock interface
+ */
+
+#ifndef _ASM_ARCH_CLK_H_
+#define _ASM_ARCH_CLK_H_
+
+static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
+{
+	return 50000000; /* 50 MHz */
+}
+
+#endif /* _ASM_ARCH_CLK_H_ */
diff --git a/arch/arm/mach-hpe/gsc/reset.c b/arch/arm/mach-hpe/gsc/reset.c
new file mode 100644
index 00000000000..67fc83b2deb
--- /dev/null
+++ b/arch/arm/mach-hpe/gsc/reset.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * GSC SoC reset
+ *
+ * (C) Copyright 2019-2025 Hewlett Packard Enterprise Development LP.
+ * Author: Gilbert Chen <gilbert.chen at hpe.com>
+ */
+
+#include <asm/io.h>
+
+#define GSC_CCR	0xC0000000
+
+void reset_cpu(void)
+{
+	writel(1, GSC_CCR);
+
+	while (1)
+		;	/* loop forever till reset */
+}

-- 
2.43.0