[PATCH 3/9] arm: dts: Add HPE GSC device tree

[Jorge Cisneros]

Add device tree for the HPE GSC SoC including:
- Dual Cortex-A35 cores with spin-table enable method
- GICv3 interrupt controller
- NS16550A compatible UART
- GXP timer and SPI/I2C controllers (shared IP blocks)
- Two Cadence GEM Ethernet MACs with SGMII PHYs
- Synopsys DWC MSHC eMMC controller
- GSC watchdog timer
- Memory-mapped virtual EEPROM for VPD storage
- Fixed clock definitions for peripheral buses

Signed-off-by: Jorge Cisneros <jorge.cisneros at hpe.com>
---
 arch/arm/dts/hpe-gsc.dts | 146 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 146 insertions(+)

diff --git a/arch/arm/dts/hpe-gsc.dts b/arch/arm/dts/hpe-gsc.dts
new file mode 100644
index 00000000000..162099c2b60
--- /dev/null
+++ b/arch/arm/dts/hpe-gsc.dts
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * GSC Device Tree
+ *
+ * (C) Copyright 2019-2025 Hewlett Packard Enterprise Development LP.
+ * Author: Gilbert Chen <gilbert.chen at hpe.com>
+ */
+
+/dts-v1/;
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "hpe,gsc";
+	model = "HPE GSC";
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+		stdout-path = &uartc;
+	};
+
+	aliases {
+		serial0 = &uartc;
+		spi0 = &spi0;
+	};
+
+	ahb at 80000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x80000000 0x52000000>;
+		ranges;
+
+		gic: gic at ce000000 {
+			compatible = "arm,gic-v3";
+			#interrupt-cells = <3>;
+			ranges;
+			interrupt-controller;
+			redistributor-stride = <0x0 0x20000>;
+			#redistributor-regions = <1>;
+			reg = <0xce000000 0x10000>,
+			      <0xce060000 0x40000>,
+			      <0xce200000 0x40000>;
+		};
+
+		timer: timer at c0000098 {
+			compatible = "hpe,gxp-timer";
+			reg = <0xc0000098 0x08>;
+			clock-frequency = <1000000>;
+		};
+
+		uartc: serial at c00000f0 {
+			compatible = "ns16550a";
+			reg = <0xc00000f0 0x8>;
+			clock-frequency = <1843212>;
+			reg-shift = <0>;
+			no-loopback-test;
+			status = "okay";
+		};
+
+		watchdog: watchdog at c0000090 {
+			compatible = "hpe,gsc-wdt";
+			reg = <0xc0000090 0x02>, <0xc0000096 0x01>;
+		};
+
+		spi0: spi at cef00000 {
+			reg = <0xcef00000 0x80>, <0xcef08000 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "hpe,gxp-spi";
+			status = "okay";
+
+			flash at 0 {
+				reg = <0>;
+				compatible = "jedec,spi-nor";
+				spi-max-frequency = <50000000>;
+			};
+
+			flash at 1 {
+				reg = <1>;
+				compatible = "jedec,spi-nor";
+				spi-max-frequency = <50000000>;
+			};
+		};
+
+		i2c2: i2c at c0002200 {
+			compatible = "hpe,gxp-i2c";
+			reg = <0xc0002200 0x70>;
+			clock-frequency = <100000>;
+			status = "okay";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			eeprom: eeprom at a0017f00 {
+				compatible = "i2c_gsc_mem_eeprom";
+				reg = <0xa0017f00 0x100>;
+			};
+		};
+
+		sdhci0: sdhci at cefe1000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xcefe1000 0x400>;
+			interrupts = <0 23 4>;
+			interrupt-parent = <&gic>;
+			clocks = <&emmcclk>;
+			clock-names = "core";
+			bus-width = <8>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			non-removable;
+			max-frequency = <200000000>;
+			mmc-hs200-1_8v;
+		};
+
+		macb0: ethernet at c0004000 {
+			compatible = "hpe,gsc-gem";
+			reg = <0xc0004000 0x1000>;
+			interrupts = <0 74 4>, <0 75 4>, <0 76 4>;
+			interrupt-parent = <&gic>;
+			phy-handle = <&ethernet_phy>;
+			clock-names = "pclk", "hclk", "tx_clk";
+			clocks = <&clk125>, <&clk125>, <&clk125>;
+			phy-mode = "sgmii";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			ethernet_phy: ethernet-phy at 0 {
+				reg = <0x0>;
+			};
+		};
+	};
+
+	clocks {
+		clk125: clk125 {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <125000000>;
+		};
+
+		emmcclk: emmcclk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <200000000>;
+			clock-output-names = "emmcclk";
+		};
+	};
+};

-- 
2.43.0