[PATCH] spi: sunxi: wait for TX/RX fifo reset done

[Yixun Lan]

Once reset SPI TX or RX fifo, the underlying hardware need to take
some time to actually settle down, the two bits will automatically
clear to 0, so use a poll mechanism to check status bits to make sure
it's done correctly.

Signed-off-by: Yixun Lan <dlan at gentoo.org>
---
On Cubie A7A board which using A733 SoC, we encoutered a SPI nor flash
timeout issue, it turns out that the SPI fifo reset take a few time to
settle down, Add a loop to poll the status.

This was the error message shows on A7A board once this issue happened.

=> sf probe
ERROR: sun4i_spi: Timeout transferring data
Failed to initialize SPI flash at 0:0 (error -2)
---
 drivers/spi/spi-sunxi.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c
index e00532a371b..cf41905c7b7 100644
--- a/drivers/spi/spi-sunxi.c
+++ b/drivers/spi/spi-sunxi.c
@@ -347,7 +347,7 @@ static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen,
 	struct sun4i_spi_priv *priv = dev_get_priv(bus);
 	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
 
-	u32 len = bitlen / 8;
+	u32 rst, val, len = bitlen / 8;
 	u8 nbytes;
 	int ret;
 
@@ -363,8 +363,11 @@ static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen,
 		sun4i_spi_set_cs(bus, slave_plat->cs[0], true);
 
 	/* Reset FIFOs */
-	setbits_le32(SPI_REG(priv, SPI_FCR), SPI_BIT(priv, SPI_FCR_RF_RST) |
-		     SPI_BIT(priv, SPI_FCR_TF_RST));
+	rst = SPI_BIT(priv, SPI_FCR_RF_RST) | SPI_BIT(priv, SPI_FCR_TF_RST);
+	setbits_le32(SPI_REG(priv, SPI_FCR), rst);
+	ret = readl_poll_timeout(SPI_REG(priv, SPI_FCR), val, !(rst & val), 20);
+	if (ret)
+		return -EBUSY;
 
 	while (len) {
 		/* Setup the transfer now... */

---
base-commit: 88dc2788777babfd6322fa655df549a019aa1e69
change-id: 20260220-02-spi-fifo-reset-25e371314c3f

Best regards,
-- 
Yixun Lan <dlan at gentoo.org>