[PATCH 3/6] arm: dts: k3-am68: ddr: Update to v0.12.0 of DDR config tool

[Neha Malcom Francis]

Hi Udit

On 21/04/26 09:20, Kumar, Udit wrote:
> 
> 
> On 10/31/2025 11:04 AM, Neha Malcom Francis wrote:
>> Update the DDR configuration for AM68 according to the SysConfig
>> DDR Configuration tool v0.12.0. Log of changes between 0.9.1 to 0.12.0
>> is [0].
>>
>> [0] https://dev.ti.com/tirex/content/TDA4x_DRA8x_AM67x-AM69x_DDR_Config_0.12.00.0000/docs/RevisionHistory.html
>>
>> Signed-off-by: Neha Malcom Francis <n-francis at ti.com>
>> ---
>>  arch/arm/dts/k3-am68-ddr-sk-lp4-4266.dtsi | 4410 +++++++++++++++++++++
>>  arch/arm/dts/k3-am68-sk-r5-base-board.dts |    2 +-
>>  2 files changed, 4411 insertions(+), 1 deletion(-)
>>  create mode 100644 arch/arm/dts/k3-am68-ddr-sk-lp4-4266.dtsi
>>
>> diff --git a/arch/arm/dts/k3-am68-ddr-sk-lp4-4266.dtsi b/arch/arm/dts/k3-am68-ddr-sk-lp4-4266.dtsi
>> new file mode 100644
>> index 00000000000..ea773a2ca4f
>> --- /dev/null
>> +++ b/arch/arm/dts/k3-am68-ddr-sk-lp4-4266.dtsi
>> @@ -0,0 +1,4410 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
>> + * This file was generated with the following tool revisions:
>> + *     - SysConfig: Revision 1.25.0+4268
>> + *     - Jacinto7_DDRSS_RegConfigTool: Revision 0.12.0
>> + * This file was generated on Thu Oct 30 2025 14:50:37 GMT+0530 (India Standard Time)
>> + *
>> + * Multi DDR Configuration (table based on register configuration tool inputs):
>> + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
>> + * | DDRSS | PHYSICAL SIZE | SOFTWARE ACCESSIBLE SIZE |
>> + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~|
>> + * |   0   |      8 GB     |           8 GB           |
>> + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~|
>> + * |   1   |      8 GB     |           8 GB           |
>> + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
>> +*/
>> +
> 
> Reviewed-by: Udit Kumar <u-kumar1 at ti.com>

Thank you for the R-by, but there was a later version:
https://lore.kernel.org/u-boot/20251103071035.674604-1-n-francis@ti.com/

But no worries, I will add the R-by when sending v3 as there are no
logical changes in this patch.

> 
>> +#define DDRSS_PLL_FHS_CNT 5
>> +#define DDRSS1_PLL_FHS_CNT 5
>> +#define DDRSS_PLL_FREQUENCY_0 27500000
>> +#define DDRSS_PLL_FREQUENCY_1 1066500000
>> +#define DDRSS_PLL_FREQUENCY_2 1066500000
>> +
> [..]
> 

-- 
Thanking You
Neha Malcom Francis