[PATCH v4 1/4] imx9: Add support for saving DDR training data to NVM

[Simona Toaca]

On Wed, Jun 03, 2026 at 06:57:14AM +0200, Marek Vasut wrote:
> On 6/2/26 4:11 PM, Marek Vasut wrote:
> > On 6/2/26 3:46 PM, Simona Toaca wrote:
> > 
> > Hi,
> > 
[...]
> > > > > +    ret = spi_flash_erase_dm(flash, offset, QB_STATE_LOAD_SIZE);
> > > > Can you please double-check whether "offset" here is always
> > > > aligned to 64
> > > > kiB (SPI NOR erase block size) ? If not, this erase here will fail.
> > > > 
> > > > Thank you
> > > 
> > > The erase size of the SPI NOR should actually be 4kiB.
> > 
> > That does not apply to all devices. I assume to align this data to 64
> > kiB offset, I would need a replacement AHAB container?
> > 
> > > I added
> > > a patch a while back enabling SFDP support, so that the erase size is
> > > parsed correctly and this does not fail. I only enabled it on U-Boot,
> > > but if you are using SPL you should enable it there too.
> > > 
> > > The only reason why I did not enable it for SPL is that there seems
> > > to not be any defconfig for iMX95/943/952 for booting from SPI NOR.
> > > 
> > > Trying 'qb save spi' from eMMC on an iMX943 EVK (with SFDP enabled):
> > > u-boot=> qb save spi
> > > SF: Detected mt35xu512aba with page size 256 Bytes, erase size 4 KiB,
> > > total 64 MiB
> > > u-boot=> echo $?
> > > 0
> > > 
> > > Without SFDP, 'sf probe' reports 128kiB erase size, not 64kiB.
> > > 
> > > I also do not see why I would check if the offset is a multiple of
> > > the erase size, since the erase fails gracefully.
> > My understanding is, that the erase operation should erase the QB data
> > from the SPI NOR, not ignore failure and keep the data there ?
If there is data in SPI NOR it means that a previous write was successful,
thus the erase shouldn't fail (as the write method in qb save also uses erase).
> 
> It seems that on iMX95 B0, the DDR_DUMMY offset is 0x76400 (aligned to 1
> kiB, which is too low):
Yes, this is indeed too low. We align our DDR_DUMMY offset to 0x1000 (4KiB) in
imx-mkimage, I see that here is not the case. At the same time, aligning
it everytime (even for eMMC/SD case) to 64KiB seems overkill.

> 
> This makes the "qb save" work reliably even on SPI NOR, because the erase
> block is aligned to 64 kiB instead of 1 kiB as it was before. Maybe we need
> such an alignment change ?

My suggestion is that we align it with what happens in imx-mkimage
and make ddr_dummy take an additional argument specifying the alignment.
(and leave 4KiB default alignment in the dtsi, which should be fine if
SFDP is used).

If you're ok with this, I will start working on a patch.

[...]

Regards,
Simona