[PATCH v4 3/9] arm: socfpga: Move firmware register settings from source code to device tree
Chee, Tien Fong
tien.fong.chee at altera.com
Wed Jun 10 10:48:46 CEST 2026
On 5/6/2026 9:54 am, alif.zakuan.yuslaimi at altera.com wrote:
> From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
>
> Migrate the CCU, firewall, and high privilege register configurations from
> hardcoded values in the source code to the device tree.
>
> L4 per/sys firewall setup which was previously done by firewall_setup() in
> spl_s10.c is now replaced by DTreg node in socfpga_soc64_u-boot.dtsi as
> Stratix10 is sharing the same tables that Agilex uses.
>
> This helps to centralize hardware configuration, improves maintainability,
> and allows easier customization for different platforms.
>
> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
> ---
>
> Changes in v4:
> - Commit message improvement
>
> arch/arm/dts/socfpga_stratix10-u-boot.dtsi | 149 +++++++++++++++++++++
> arch/arm/mach-socfpga/spl_s10.c | 29 ++--
> drivers/ddr/altera/sdram_s10.c | 44 ------
> 3 files changed, 165 insertions(+), 57 deletions(-)
>
> diff --git a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
> index a3b4c0564f9..ad4b383f704 100644
> --- a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
> +++ b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
> @@ -6,6 +6,7 @@
> * Copyright (C) 2026 Altera Corporation <www.altera.com>
> */
>
> +#include "socfpga_soc64_u-boot.dtsi"
> #include "socfpga_soc64_fit-u-boot.dtsi"
>
> /{
> @@ -134,6 +135,154 @@
> bootph-all;
> };
>
> +&socfpga_l3interconnect_firewall {
> + i_ccu_noc_registers at f7000000 {
> + reg = <0xf7000000 0x00049e60>;
> + intel,offset-settings =
> + /* Enable access to DDR reg from CPU */
> + <0x0004400 0xF8000000 0xffffffff>,
> +
> + /* Enable access to DDR region from CPU */
> + <0x00045c0 0x00000000 0xffffffdf>,
> + <0x00045e0 0x00000000 0xffffffdf>,
> + <0x0004600 0x00000000 0xffffffdf>,
> + <0x0004620 0x00000000 0xffffffdf>,
> + <0x0004640 0x00000000 0xffffffdf>,
> + <0x0004660 0x00000000 0xffffffdf>,
> +
> + /* Disable ocram security at CCU for non secure access */
> + <0x0004688 0xfffc0000 0xffffffcf>,
> + <0x0018628 0xfffc0000 0xffffffcf>,
> +
> + /* Enable access to DDR region from IO master */
> + <0x00018560 0x00000000 0xffffffdf>,
> + <0x00018580 0x00000000 0xffffffdf>,
> + <0x000185a0 0x00000000 0xffffffdf>,
> + <0x000185c0 0x00000000 0xffffffdf>,
> + <0x000185e0 0x00000000 0xffffffdf>,
> + <0x00018600 0x00000000 0xffffffdf>,
> +
> + /* Enable access to DDR region from TCU */
> + <0x0002c520 0x00000000 0xffffffdf>,
> + <0x0002c540 0x00000000 0xffffffdf>,
> + <0x0002c560 0x00000000 0xffffffdf>,
> + <0x0002c580 0x00000000 0xffffffdf>,
> + <0x0002c5a0 0x00000000 0xffffffdf>,
> + <0x0002c5c0 0x00000000 0xffffffdf>,
> +
> + /* Enable access to DDR region from FPGA */
> + <0x000105a0 0x00000000 0xffffffdf>,
> + <0x000105c0 0x00000000 0xffffffdf>,
> + <0x000105e0 0x00000000 0xffffffdf>,
> + <0x00010600 0x00000000 0xffffffdf>,
> + <0x00010620 0x00000000 0xffffffdf>,
> + <0x00010640 0x00000000 0xffffffdf>;
> + bootph-all;
> + };
> +
> + /*
> + * Both firewall and QOS regs accessed by CPU in MPFE has
> + * dependency on CCU configuration above.
> + *
> + * Below are all fpga2sdram firewall settings with default
> + * reset value for the sake of easy reference by users.
> + * Users may choose to remove any of these register configurations
> + * that they do not require in their specific implementation.
> + */
> + soc_noc_fw_ddr_fpga2sdram_inst_0_ddr_scr at f8020200 {
> + reg = <0xf8020200 0x00000050>;
> + intel,offset-settings =
> + <0x0000000 0x00000000 0x0000000f>,
> + <0x0000004 0x00000000 0x0000000f>,
> + <0x0000008 0x00000000 0x0000000f>,
> + <0x0000010 0x00000000 0xffff0000>,
> + <0x0000014 0x00000000 0x0000001f>,
> + <0x0000018 0x00000000 0xffff0000>,
> + <0x000001c 0x00000000 0x0000001f>,
> + <0x0000020 0x00000000 0xffff0000>,
> + <0x0000024 0x00000000 0x0000001f>,
> + <0x0000028 0x00000000 0xffff0000>,
> + <0x000002c 0x00000000 0x0000001f>,
> + <0x0000030 0x00000000 0xffff0000>,
> + <0x0000034 0x00000000 0x0000001f>,
> + <0x0000038 0x00000000 0xffff0000>,
> + <0x000003c 0x00000000 0x0000001f>,
> + <0x0000040 0x00000000 0xffff0000>,
> + <0x0000044 0x00000000 0x0000001f>,
> + <0x0000048 0x00000000 0xffff0000>,
> + <0x000004c 0x00000000 0x0000001f>;
> + bootph-all;
> + };
> +
> + soc_noc_fw_ddr_fpga2sdram_inst_1_ddr_scr at f8020300 {
> + reg = <0xf8020300 0x00000050>;
> + intel,offset-settings =
> + <0x0000000 0x00000000 0x0000000f>,
> + <0x0000004 0x00000000 0x0000000f>,
> + <0x0000008 0x00000000 0x0000000f>,
> + <0x0000010 0x00000000 0xffff0000>,
> + <0x0000014 0x00000000 0x0000001f>,
> + <0x0000018 0x00000000 0xffff0000>,
> + <0x000001c 0x00000000 0x0000001f>,
> + <0x0000020 0x00000000 0xffff0000>,
> + <0x0000024 0x00000000 0x0000001f>,
> + <0x0000028 0x00000000 0xffff0000>,
> + <0x000002c 0x00000000 0x0000001f>,
> + <0x0000030 0x00000000 0xffff0000>,
> + <0x0000034 0x00000000 0x0000001f>,
> + <0x0000038 0x00000000 0xffff0000>,
> + <0x000003c 0x00000000 0x0000001f>,
> + <0x0000040 0x00000000 0xffff0000>,
> + <0x0000044 0x00000000 0x0000001f>,
> + <0x0000048 0x00000000 0xffff0000>,
> + <0x000004c 0x00000000 0x0000001f>;
> + bootph-all;
> + };
> +
> + soc_noc_fw_ddr_fpga2sdram_inst_2_ddr_scr at f8020400 {
> + reg = <0xf8020400 0x00000050>;
> + intel,offset-settings =
> + <0x0000000 0x00000000 0x0000000f>,
> + <0x0000004 0x00000000 0x0000000f>,
> + <0x0000008 0x00000000 0x0000000f>,
> + <0x0000010 0x00000000 0xffff0000>,
> + <0x0000014 0x00000000 0x0000001f>,
> + <0x0000018 0x00000000 0xffff0000>,
> + <0x000001c 0x00000000 0x0000001f>,
> + <0x0000020 0x00000000 0xffff0000>,
> + <0x0000024 0x00000000 0x0000001f>,
> + <0x0000028 0x00000000 0xffff0000>,
> + <0x000002c 0x00000000 0x0000001f>,
> + <0x0000030 0x00000000 0xffff0000>,
> + <0x0000034 0x00000000 0x0000001f>,
> + <0x0000038 0x00000000 0xffff0000>,
> + <0x000003c 0x00000000 0x0000001f>,
> + <0x0000040 0x00000000 0xffff0000>,
> + <0x0000044 0x00000000 0x0000001f>,
> + <0x0000048 0x00000000 0xffff0000>,
> + <0x000004c 0x00000000 0x0000001f>;
> + bootph-all;
> + };
> +
> + /*
> + * Example of ccu_mem0_I_main QOS settings with
> + * default reset value for the sake of easy reference
> + * by users. Users may choose to remove any of these register
> + * configurations that they do not require in their specific
> + * implementation.
> + */
> + soc_ddr_scheduler_inst_0_ccu_mem0_I_main_QosGenerator at f8022080 {
> + reg = <0xf8022080 0x0000001c>;
> + intel,offset-settings =
> + <0x0000008 0x00000000 0x00000303>,
> + <0x000000c 0x00000001 0x00000003>,
> + <0x0000010 0x00000BFE 0x00001fff>,
> + <0x0000014 0x00000008 0x000003ff>,
> + <0x0000018 0x00000000 0x00000007>;
> + bootph-all;
> + };
> +};
> +
> &uart0 {
> bootph-all;
> clock-frequency = <100000000>;
> diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
> index a0d3c96d456..8ab80740c6e 100644
> --- a/arch/arm/mach-socfpga/spl_s10.c
> +++ b/arch/arm/mach-socfpga/spl_s10.c
> @@ -25,6 +25,7 @@ void board_init_f(ulong dummy)
> {
> const struct cm_config *cm_default_cfg = cm_get_default_config();
> int ret;
> + struct udevice *dev;
>
> ret = spl_early_init();
> if (ret)
> @@ -67,22 +68,24 @@ void board_init_f(ulong dummy)
> print_reset_info();
> cm_print_clock_quick_summary();
>
> - firewall_setup();
> + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-system-mgr-firewall", &dev);
> + if (ret) {
> + printf("System manager firewall configuration failed: %d\n", ret);
> + hang();
> + }
>
> - /* disable ocram security at CCU for non secure access */
> - clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0),
> - CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
> - clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0),
> - CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
> + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-l3interconnect-firewall", &dev);
> + if (ret) {
> + printf("L3 interconnect firewall configuration failed: %d\n", ret);
> + hang();
> + }
>
> #if CONFIG_IS_ENABLED(ALTERA_SDRAM)
> - struct udevice *dev;
> -
> - ret = uclass_get_device(UCLASS_RAM, 0, &dev);
> - if (ret) {
> - debug("DRAM init failed: %d\n", ret);
> - hang();
> - }
> + ret = uclass_get_device(UCLASS_RAM, 0, &dev);
> + if (ret) {
> + debug("DRAM init failed: %d\n", ret);
> + hang();
> + }
> #endif
>
> #ifdef CONFIG_CADENCE_QSPI
> diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
> index 4ac4c79e0ac..1497a8e4aab 100644
> --- a/drivers/ddr/altera/sdram_s10.c
> +++ b/drivers/ddr/altera/sdram_s10.c
> @@ -78,50 +78,6 @@ int sdram_mmr_init_full(struct udevice *dev)
> phys_size_t hw_size;
> struct bd_info bd = {0};
>
> - /* Enable access to DDR from CPU master */
> - clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_DDRREG),
> - CCU_ADBASE_DI_MASK);
> - clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE0),
> - CCU_ADBASE_DI_MASK);
> - clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1A),
> - CCU_ADBASE_DI_MASK);
> - clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1B),
> - CCU_ADBASE_DI_MASK);
> - clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1C),
> - CCU_ADBASE_DI_MASK);
> - clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1D),
> - CCU_ADBASE_DI_MASK);
> - clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1E),
> - CCU_ADBASE_DI_MASK);
> -
> - /* Enable access to DDR from IO master */
> - clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE0),
> - CCU_ADBASE_DI_MASK);
> - clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1A),
> - CCU_ADBASE_DI_MASK);
> - clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1B),
> - CCU_ADBASE_DI_MASK);
> - clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1C),
> - CCU_ADBASE_DI_MASK);
> - clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1D),
> - CCU_ADBASE_DI_MASK);
> - clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1E),
> - CCU_ADBASE_DI_MASK);
> -
> - /* Enable access to DDR from TCU */
> - clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE0),
> - CCU_ADBASE_DI_MASK);
> - clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1A),
> - CCU_ADBASE_DI_MASK);
> - clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1B),
> - CCU_ADBASE_DI_MASK);
> - clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1C),
> - CCU_ADBASE_DI_MASK);
> - clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1D),
> - CCU_ADBASE_DI_MASK);
> - clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1E),
> - CCU_ADBASE_DI_MASK);
> -
> /* this enables nonsecure access to DDR */
> /* mpuregion0addr_limit */
> FW_MPU_DDR_SCR_WRITEL(0xFFFF0000, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
Reviewed-by: Tien Fong Chee <tien.fong.chee at altera.com>
Best regards,
Tien Fong
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