[PATCH 1/2] rockchip: rk3568: make the WDT trigger a first global reset

[Jonas Karlman]

Hi Andreas,

On 6/20/2026 12:08 AM, Andreas Zdziarstek wrote:
> Default is a second global reset which causes a system hang on a timeout
> in U-Boot.
> 
> Verified on the Hardkernel ODROID-M1S (RK3566): a watchdog timeout now
> cleanly reboots the board.
> 
> Signed-off-by: Andreas Zdziarstek <andreas.zdziarstek at gmail.com>
> ---
>  arch/arm/mach-rockchip/rk3568/rk3568.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c
> index 2b1eafee37c..77610a6a6ec 100644
> --- a/arch/arm/mach-rockchip/rk3568/rk3568.c
> +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
> @@ -37,6 +37,10 @@
>  #define CPU_GRF_BASE		0xfdc30000
>  #define GRF_CORE_PVTPLL_CON0	(0x10)
>  
> +#define CRU_BASE		0xfdd20000
> +#define CRU_GLB_RST_CON		(CRU_BASE + 0x0dc)
> +#define WDT_GLB_SRST_CTRL	BIT(1)
> +
>  /* PMU_GRF_GPIO0D_IOMUX_L */
>  enum {
>  	GPIO0D1_SHIFT		= 4,
> @@ -146,6 +150,10 @@ int arch_cpu_init(void)
>  	writel((PMU_PD_VO_DWN_ENA << 16),
>  	       PMU_BASE_ADDR + PMU_PWR_GATE_SFTCON);
>  #endif
> +
> +	/* Make WDT trigger a first global reset */
> +	setbits_le32((void __iomem *)CRU_GLB_RST_CON, WDT_GLB_SRST_CTRL);

It should likely be enough to configure this in XPL_BUILD?

We should possibly also clear SOC_CON1 to handle reset in similar way as
TF-A / PSCI reset. RK356x boards use PSCI reset in U-Boot proper
primarily to work around issues found when working on [1], using first
global reset seemed to wipe too much information we may want to retain.

[1] https://lore.kernel.org/u-boot/20240202001221.531207-1-jonas@kwiboo.se/

Regards,
Jonas

> +
>  	return 0;
>  }
>