[PATCH v2] riscv: Skip riscv_cpu_setup() when CPU driver is disabled

Tom Rini trini at konsulko.com
Mon Jun 29 16:28:51 CEST 2026


On Mon, Jun 29, 2026 at 11:00:40AM +0200, Michal Simek wrote:
> Hi Tom,
> 
> On 5/11/26 10:31, Michal Simek wrote:
> > Building on commit c64fc632a86a ("riscv: cpu: Use CONFIG_IS_ENABLED(CPU)
> > instead of plain ifdef"), add an early return in riscv_cpu_setup() when
> > CONFIG_CPU is not enabled. This allows platforms to save code space in
> > SPL by disabling CONFIG_SPL_CPU.
> > 
> > Without this patch, building U-Boot with CONFIG_CPU=n and CONFIG_EVENT=y
> > is broken: riscv_cpu_setup() is registered as an EVT_DM_POST_INIT_F event
> > spy, and when the CPU uclass is unavailable uclass_find_first_device()
> > returns no device, so the function returns -ENODEV. That in turn makes
> > event_notify_null() in dm_init_and_scan() fail and triggers a boot hang
> > ("initcall initf_dm() failed"). Returning 0 early avoids that failure.
> > 
> > The compiler's dead-code elimination combined with --gc-sections
> > removes the unreachable code and all associated static data,
> > achieving significant size reduction without preprocessor guards:
> > 
> >    spl/u-boot-spl:all -4332 spl/u-boot-spl:rodata -2872
> >    spl/u-boot-spl:text -1460
> > 
> > Signed-off-by: Michal Simek <michal.simek at amd.com>
> > Reviewed-by: Yao Zi <me at ziyao.cc>
> > ---
> > 
> > Changes in v2:
> > - extend commit message
> > 
> >   arch/riscv/cpu/cpu.c | 3 +++
> >   1 file changed, 3 insertions(+)
> > 
> > diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> > index bbadd0c9a469..3bec7c7cb6d0 100644
> > --- a/arch/riscv/cpu/cpu.c
> > +++ b/arch/riscv/cpu/cpu.c
> > @@ -638,6 +638,9 @@ int riscv_cpu_setup(void)
> >   	const char *isa, **exts;
> >   	struct udevice *dev;
> > +	if (!CONFIG_IS_ENABLED(CPU))
> > +		return 0;
> > +
> >   	uclass_find_first_device(UCLASS_CPU, &dev);
> >   	if (!dev) {
> >   		debug("unable to find the RISC-V cpu device\n");
> 
> Can you please take it directly to next branch?

I understand your frustration at how the RISC-V changes have been being
handled for several months now. I'm adding the new custodian (Tim) as
well as Leo's new email to the email here as I expect a pull request for
the next branch (and I can help with questions on "how", off-list, if
needed), hopefully soon.

-- 
Tom
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