[U-Boot] [PATCH 2/6] AVR32: Support for external SRAM on at32uc3
Gunnar Rangoy
gunnar at rangoy.com
Thu Nov 13 16:25:08 CET 2008
This patch adds support for external SRAM connected to the EBI bus
on the at32uc3a0xxx.
Signed-off-by: Gunnar Rangoy <gunnar at rangoy.com>
Signed-off-by: Paul Driveklepp <pauldriveklepp at gmail.com>
Signed-off-by: Olav Morken <olavmrk at gmail.com>
---
cpu/at32uc/Makefile | 1 +
cpu/at32uc/smc.c | 61 ++++++++++++++++++++++++++
cpu/at32uc/smc.h | 105 ++++++++++++++++++++++++++++++++++++++++++++++
include/asm-avr32/sram.h | 34 +++++++++++++++
4 files changed, 201 insertions(+), 0 deletions(-)
create mode 100644 cpu/at32uc/smc.c
create mode 100644 cpu/at32uc/smc.h
create mode 100644 include/asm-avr32/sram.h
diff --git a/cpu/at32uc/Makefile b/cpu/at32uc/Makefile
index cab9bdc..6714d14 100644
--- a/cpu/at32uc/Makefile
+++ b/cpu/at32uc/Makefile
@@ -36,6 +36,7 @@ COBJS-y += cache.o
COBJS-y += interrupts.o
COBJS-$(CONFIG_PORTMUX_GPIO) += portmux-gpio.o
COBJS-y += flashc.o
+COBJS-y += smc.o
SRCS := $(START-y:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
diff --git a/cpu/at32uc/smc.c b/cpu/at32uc/smc.c
new file mode 100644
index 0000000..f4bb9fb
--- /dev/null
+++ b/cpu/at32uc/smc.c
@@ -0,0 +1,61 @@
+#include <common.h>
+#include <asm/sram.h>
+#include "smc.h"
+
+unsigned long sram_init(const struct sram_config *config)
+{
+ u32 cfgreg;
+ u32 dbw;
+ u32 sram_size;
+
+ cfgreg = SMC_BF(NWE_SETUP, config->nwe_setup)
+ |SMC_BF(NRD_SETUP, config->nrd_setup)
+ |SMC_BF(NCS_WR_SETUP, config->ncs_wr_setup)
+ |SMC_BF(NCS_RD_SETUP, config->ncs_rd_setup);
+ smc_writel(config->chip_select, SETUP, cfgreg);
+
+ cfgreg = SMC_BF(NWE_PULSE, config->nwe_pulse)
+ |SMC_BF(NRD_PULSE, config->nrd_pulse)
+ |SMC_BF(NCS_WR_PULSE, config->ncs_wr_pulse)
+ |SMC_BF(NCS_RD_PULSE, config->ncs_rd_pulse);
+ smc_writel(config->chip_select, PULSE, cfgreg);
+
+ cfgreg = SMC_BF(NWE_CYCLE, config->nwe_cycle)
+ |SMC_BF(NRD_CYCLE, config->nrd_cycle);
+ smc_writel(config->chip_select, CYCLE, cfgreg);
+
+ switch (config->data_bits) {
+ case 8:
+ dbw=0;
+ break;
+ case 16:
+ dbw=1;
+ break;
+ case 32:
+ dbw=2;
+ break;
+ default:
+ panic("Invalid number of databits for SRAM");
+
+ }
+ cfgreg = SMC_BF(READ_MODE, config->read_mode)
+ |SMC_BF(WRITE_MODE, config->write_mode)
+ |SMC_BF(EXNW_MODE, config->exnw_mode)
+ |SMC_BF(BAT, config->bat)
+ |SMC_BF(DBW, dbw)
+ |SMC_BF(TDF_CYCLES, config->tdf_cycles)
+ |SMC_BF(TDF_MODE, config->tdf_mode)
+ |SMC_BF(PMEN, config->pmen)
+ |SMC_BF(PS, config->ps);
+
+
+
+
+ smc_writel(config->chip_select, MODE, cfgreg);
+ sram_size= (1<<config->address_bits) * (config->data_bits/8);
+
+
+ return sram_size;
+}
+
+
diff --git a/cpu/at32uc/smc.h b/cpu/at32uc/smc.h
new file mode 100644
index 0000000..ea4d399
--- /dev/null
+++ b/cpu/at32uc/smc.h
@@ -0,0 +1,105 @@
+/*
+ * Register definitions for Static Memory Controller
+ */
+#ifndef __CPU_AT32UC3_SMC_H__
+#define __CPU_AT32UC3_SMC_H__
+
+#include <asm/arch/memory-map.h>
+#include <asm/io.h>
+
+/* SMC register offsets */
+#define SMC_SETUP(x) 0x0000+(x)*0x10
+#define SMC_PULSE(x) 0x0004+(x)*0x10
+#define SMC_CYCLE(x) 0x0008+(x)*0x10
+#define SMC_MODE(x) 0x000c+(x)*0x10
+
+/* Bitfields in SETUP0..3 */
+#define SMC_NWE_SETUP_OFFSET 0
+#define SMC_NWE_SETUP_SIZE 6
+#define SMC_NCS_WR_SETUP_OFFSET 8
+#define SMC_NCS_WR_SETUP_SIZE 6
+#define SMC_NRD_SETUP_OFFSET 16
+#define SMC_NRD_SETUP_SIZE 6
+#define SMC_NCS_RD_SETUP_OFFSET 24
+#define SMC_NCS_RD_SETUP_SIZE 6
+
+/* Bitfields in PULSE0..3 */
+#define SMC_NWE_PULSE_OFFSET 0
+#define SMC_NWE_PULSE_SIZE 7
+#define SMC_NCS_WR_PULSE_OFFSET 8
+#define SMC_NCS_WR_PULSE_SIZE 7
+#define SMC_NRD_PULSE_OFFSET 16
+#define SMC_NRD_PULSE_SIZE 7
+#define SMC_NCS_RD_PULSE_OFFSET 24
+#define SMC_NCS_RD_PULSE_SIZE 7
+
+/* Bitfields in CYCLE0..3 */
+#define SMC_NWE_CYCLE_OFFSET 0
+#define SMC_NWE_CYCLE_SIZE 9
+#define SMC_NRD_CYCLE_OFFSET 16
+#define SMC_NRD_CYCLE_SIZE 9
+
+/* Bitfields in MODE0..3 */
+#define SMC_READ_MODE_OFFSET 0
+#define SMC_READ_MODE_SIZE 1
+#define SMC_WRITE_MODE_OFFSET 1
+#define SMC_WRITE_MODE_SIZE 1
+#define SMC_EXNW_MODE_OFFSET 4
+#define SMC_EXNW_MODE_SIZE 2
+#define SMC_BAT_OFFSET 8
+#define SMC_BAT_SIZE 1
+#define SMC_DBW_OFFSET 12
+#define SMC_DBW_SIZE 2
+#define SMC_TDF_CYCLES_OFFSET 16
+#define SMC_TDF_CYCLES_SIZE 4
+#define SMC_TDF_MODE_OFFSET 20
+#define SMC_TDF_MODE_SIZE 1
+#define SMC_PMEN_OFFSET 24
+#define SMC_PMEN_SIZE 1
+#define SMC_PS_OFFSET 28
+#define SMC_PS_SIZE 2
+
+/* Constants for READ_MODE */
+#define SMC_READ_MODE_NCS_CONTROLLED 0
+#define SMC_READ_MODE_NRD_CONTROLLED 1
+
+/* Constants for WRITE_MODE */
+#define SMC_WRITE_MODE_NCS_CONTROLLED 0
+#define SMC_WRITE_MODE_NWE_CONTROLLED 1
+
+/* Constants for EXNW_MODE */
+#define SMC_EXNW_MODE_DISABLED 0
+#define SMC_EXNW_MODE_RESERVED 1
+#define SMC_EXNW_MODE_FROZEN 2
+#define SMC_EXNW_MODE_READY 3
+
+/* Constants for BAT */
+#define SMC_BAT_BYTE_SELECT 0
+#define SMC_BAT_BYTE_WRITE 1
+
+/* Constants for DBW */
+#define SMC_DBW_8_BITS 0
+#define SMC_DBW_16_BITS 1
+#define SMC_DBW_32_BITS 2
+
+/* Bit manipulation macros */
+#define SMC_BIT(name) \
+ (1 << SMC_##name##_OFFSET)
+#define SMC_BF(name,value) \
+ (((value) & ((1 << SMC_##name##_SIZE) - 1)) \
+ << SMC_##name##_OFFSET)
+#define SMC_BFEXT(name,value) \
+ (((value) >> SMC_##name##_OFFSET) \
+ & ((1 << SMC_##name##_SIZE) - 1))
+#define SMC_BFINS(name,value,old)\
+ (((old) & ~(((1 << SMC_##name##_SIZE) - 1) \
+ << SMC_##name##_OFFSET)) \
+ | SMC_BF(name,value))
+
+/* Register access macros */
+#define smc_readl(cs,reg) \
+ readl((void *)SMC_BASE + SMC_##reg(cs))
+#define smc_writel(cs,reg,value) \
+ writel((value), (void *)SMC_BASE + SMC_##reg(cs))
+
+#endif /* __CPU_AT32UC3_SMC_H__ */
diff --git a/include/asm-avr32/sram.h b/include/asm-avr32/sram.h
new file mode 100644
index 0000000..3306d0b
--- /dev/null
+++ b/include/asm-avr32/sram.h
@@ -0,0 +1,34 @@
+#ifndef __ASM_AVR32_SRAM_H
+#define __ASM_AVR32_SRAM_H
+#include <asm/types.h>
+
+struct sram_config {
+ /* Number of data bits. */
+ u8 data_bits;
+
+ /* Chip select */
+ u8 chip_select;
+
+ /* Number of address bits */
+ u8 address_bits;
+
+ /* nwe/nrd waveforms */
+ u8 nwe_setup, nwe_pulse, nwe_hold;
+ u8 nrd_setup, nrd_pulse, nrd_hold;
+
+ /* ncs waveforms */
+ u8 ncs_wr_setup, ncs_wr_pulse, ncs_wr_hold;
+ u8 ncs_rd_setup, ncs_rd_pulse, ncs_rd_hold;
+
+ /* Cycle length */
+ u16 nwe_cycle, nrd_cycle;
+
+ /* mode */
+ u8 read_mode, write_mode, exnw_mode;
+ u8 bat, dbw, tdf_cycles, tdf_mode, pmen, ps;
+};
+
+
+unsigned long sram_init(const struct sram_config *config);
+
+#endif /* __ASM_AVR32_SRAM_H */
--
1.5.6.3
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