[U-Boot] [PATCH 1/2] Create the S5PC100 SoC code under the cpu/arm_cortesa8/
Kim, Heung Jun
riverful at gmail.com
Tue Jun 2 14:51:27 CEST 2009
Signed-off-by: HeungJun, Kim <riverful.kim at samsung.com>
---
This patch is the new processor - S5PC100's SoC code & headers.
This patch consists of 2 files.
The First file is to create the new SoC code related with S5PC100
application processor.
It's located in ther cpu/arm_cortesa8/s5pc100.
The Second file is to create the new SoC header related with S5PC100
application processor.
It's located in ther include/asm-arm/s5pc100.
This file is the First.
cpu/arm_cortexa8/s5pc100/Makefile | 48 +++++++
cpu/arm_cortexa8/s5pc100/config.mk | 36 ++++++
cpu/arm_cortexa8/s5pc100/cpu_init.S | 196 +++++++++++++++++++++++++++++
cpu/arm_cortexa8/s5pc100/interrupts.c | 218 +++++++++++++++++++++++++++++++++
cpu/arm_cortexa8/s5pc100/speed.c | 159 ++++++++++++++++++++++++
5 files changed, 657 insertions(+), 0 deletions(-)
create mode 100644 cpu/arm_cortexa8/s5pc100/Makefile
create mode 100644 cpu/arm_cortexa8/s5pc100/config.mk
create mode 100644 cpu/arm_cortexa8/s5pc100/cpu_init.S
create mode 100644 cpu/arm_cortexa8/s5pc100/interrupts.c
create mode 100644 cpu/arm_cortexa8/s5pc100/speed.c
diff --git a/cpu/arm_cortexa8/s5pc100/Makefile
b/cpu/arm_cortexa8/s5pc100/Makefile
new file mode 100644
index 0000000..4688533
--- /dev/null
+++ b/cpu/arm_cortexa8/s5pc100/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg at denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).a
+
+COBJS-y = interrupts.o
+COBJS-$(CONFIG_S5PC100) += cpu_init.o speed.o
+
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/cpu/arm_cortexa8/s5pc100/config.mk
b/cpu/arm_cortexa8/s5pc100/config.mk
new file mode 100644
index 0000000..e05d7ae
--- /dev/null
+++ b/cpu/arm_cortexa8/s5pc100/config.mk
@@ -0,0 +1,36 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj at denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
+ -msoft-float
+
+# Make ARMv5 to allow more compilers to work, even though its v6.
+PLATFORM_CPPFLAGS += -march=armv5t
+# =========================================================================
+#
+# Supply options according to compiler version
+#
+# =========================================================================
+PLATFORM_CPPFLAGS +=$(call cc-option)
+PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
+PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\
+ $(call cc-option,-malignment-traps,))
diff --git a/cpu/arm_cortexa8/s5pc100/cpu_init.S
b/cpu/arm_cortexa8/s5pc100/cpu_init.S
new file mode 100644
index 0000000..4510049
--- /dev/null
+++ b/cpu/arm_cortexa8/s5pc100/cpu_init.S
@@ -0,0 +1,196 @@
+/*
+ * Originates from Samsung's u-boot 1.1.6 port to S5PC1xx
+ *
+ * Copyright (C) 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg at denx.de>
+
+ * Copyright (C) 2009
+ * Inki Dae, SAMSUNG Electronics, <inki.dae at samsung.com>
+ * Heungjun Kim, SAMSUNG Electronics, <riverful.kim at samsung.com>
+ * Minkyu Kang, SAMSUNG Electronics, <mk7.kang at samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+ .globl mem_ctrl_asm_init
+mem_ctrl_asm_init:
+
+#ifdef CONFIG_ONENAND_IPL
+ /* DLL parameter setting */
+ ldr r0, =S5P_PHYCONTROL0 @ 0xe6000018
+ ldr r1, =0x50101000
+ str r1, [r0]
+#endif
+
+#ifndef CONFIG_ONENAND_IPL
+ ldr r0, =S5P_PHYCONTROL1 @ 0xe600001c
+ ldr r1, =0xf4
+ str r1, [r0]
+
+ ldr r0, =S5P_PHYCONTROL2 @ 0xe6000020
+ ldr r1, =0x0
+ str r1, [r0]
+
+ /* DLL on */
+ ldr r0, =S5P_PHYCONTROL0 @ 0xe6000018
+ ldr r1, =0x50101002
+ str r1, [r0]
+
+ /* DLL start */
+ ldr r0, =S5P_PHYCONTROL0 @ 0xe6000018
+ ldr r1, =0x50101003
+ str r1, [r0]
+
+ /* Force value locking for DLL off */
+ ldr r0, =S5P_PHYCONTROL0 @ 0xe6000018
+ ldr r1, =0x50101003
+ str r1, [r0]
+
+ /* DLL off */
+ ldr r0, =S5P_PHYCONTROL0 @ 0xe6000018
+ ldr r1, =0x50101001
+ str r1, [r0]
+
+ /* auto refresh off */
+ ldr r0, =S5P_CONCONTROL @ 0xe6000000
+ ldr r1, =0xff001010
+ str r1, [r0]
+#endif
+
+#ifdef CONFIG_ONENAND_IPL
+ /*
+ * BL%LE %LONG4, 2 chip, LPDDR, dynamic self refresh,
+ * force precharge, dynamic power down off
+ */
+ ldr r0, =S5P_MEMCONTROL @ 0xe6000004
+ ldr r1, =0x00212100
+ str r1, [r0]
+
+ /* 128MB config, 4banks */
+ ldr r0, =S5P_MEMCONFIG0 @ 0xe6000008
+ ldr r1, =0x20f80222
+ str r1, [r0]
+#endif
+
+#ifndef CONFIG_ONENAND_IPL
+ ldr r0, =S5P_MEMCONFIG1 @ 0xe600000c
+ ldr r1, =0x28f80222
+ str r1, [r0]
+
+ ldr r0, =S5P_PRECHCONFIG @ 0xe6000014
+ ldr r1, =0x20000000
+ str r1, [r0]
+#endif
+
+#ifdef CONFIG_ONENAND_IPL
+ /*
+ * 7.8us*166MHz%LE %LONG1294(0x50E) 7.8us*133MHz%LE %LONG1038(0x40E),
+ * 100MHz%LE %LONG780(0x30C),
+ * 20MHz%LE %LONG156(0x9C),
+ * 10MHz%LE %LONG78(0x4E)
+ */
+ ldr r0, =S5P_TIMINGAREF @ 0xe6000030
+ ldr r1, =0x0000050e
+ str r1, [r0]
+
+ /* 133MHz */
+ ldr r0, =S5P_TIMINGROW @ 0xe6000034
+ ldr r1, =0x0c233287
+ str r1, [r0]
+
+ /* twtr=3 twr=2 trtp=3 cl=3 wl=3 rl=3 */
+ ldr r0, =S5P_TIMINGDATA @ 0xe6000038
+ ldr r1, =0x32330303
+ str r1, [r0]
+
+ /* tfaw=4 sxsr=0x14 txp=0x14 tcke=3 tmrd=3 */
+ ldr r0, =S5P_TIMINGPOWER @ 0xe600003c
+ ldr r1, =0x04141433
+ str r1, [r0]
+
+ /* chip0 Deselect */
+ ldr r0, =S5P_DIRECTCMD @ 0xe6000010
+ ldr r1, =0x07000000
+ str r1, [r0]
+
+ /* chip0 PALL */
+ ldr r0, =S5P_DIRECTCMD @ 0xe6000010
+ ldr r1, =0x01000000
+ str r1, [r0]
+
+ /* chip0 REFA */
+ ldr r0, =S5P_DIRECTCMD @ 0xe6000010
+ ldr r1, =0x05000000
+ str r1, [r0]
+
+ /* chip0 REFA */
+ ldr r0, =S5P_DIRECTCMD @ 0xe6000010
+ ldr r1, =0x05000000
+ str r1, [r0]
+
+ /* chip0 MRS, CL%LE %LONG3, BL%LE %LONG4 */
+ ldr r0, =S5P_DIRECTCMD @ 0xe6000010
+ ldr r1, =0x00000032
+ str r1, [r0]
+#endif
+
+#ifndef CONFIG_ONENAND_IPL
+ /* chip1 Deselect */
+ ldr r0, =S5P_DIRECTCMD @ 0xe6000010
+ ldr r1, =0x07100000
+ str r1, [r0]
+
+ /* chip1 PALL */
+ ldr r0, =S5P_DIRECTCMD @ 0xe6000010
+ ldr r1, =0x01100000
+ str r1, [r0]
+
+ /* chip1 REFA */
+ ldr r0, =S5P_DIRECTCMD @ 0xe6000010
+ ldr r1, =0x05100000
+ str r1, [r0]
+
+ /* chip1 REFA */
+ ldr r0, =S5P_DIRECTCMD @ 0xe6000010
+ ldr r1, =0x05100000
+ str r1, [r0]
+
+ /* chip1 MRS, CL%LE %LONG3, BL%LE %LONG4 */
+ ldr r0, =S5P_DIRECTCMD @ 0xe6000010
+ ldr r1, =0x00100032
+ str r1, [r0]
+
+ /* auto refresh on */
+ ldr r0, =S5P_CONCONTROL @ 0xe6000000
+ ldr r1, =0xff002030
+ str r1, [r0]
+
+#endif
+
+#ifdef CONFIG_ONENAND_IPL
+ /* BL%LE %LONG */
+ ldr r0, =S5P_MEMCONTROL @ 0xe6000004
+ ldr r1, =0xff212100
+ str r1, [r0]
+#endif
+ mov pc, lr
+
+ .ltorg
diff --git a/cpu/arm_cortexa8/s5pc100/interrupts.c
b/cpu/arm_cortexa8/s5pc100/interrupts.c
new file mode 100644
index 0000000..3d2a2e5
--- /dev/null
+++ b/cpu/arm_cortexa8/s5pc100/interrupts.c
@@ -0,0 +1,218 @@
+/*
+ * (C) Copyright 2003
+ * Texas Instruments <www.ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger at sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu at sysgo.de>
+ *
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, <gj at denx.de>
+ *
+ * (C) Copyright 2004
+ * Philippe Robin, ARM Ltd. <philippe.robin at arm.com>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg at denx.de>
+ *
+ * (C) Copyright 2009
+ * Heungjun Kim, SAMSUNG Electronics, <riverful.kim at samsung.com>
+ * Inki Dae, SAMSUNG Electronics, <inki.dae at samsung.com>
+ * Minkyu Kang, SAMSUNG Electronics, <mk7.kang at samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+
+#define PRESCALER_0 (16 - 1) /* prescaler of PWM timer 4 */
+#define MUX4_DIV_12 (2 - 1) /* MUX 4, 1/2 period */
+
+static ulong count_value;
+
+/* Internal tick units */
+static unsigned long long timestamp; /* Monotonic incrementing timer */
+static unsigned long lastdec; /* Last decremneter snapshot */
+
+/* macro to read the 16 bit timer */
+static inline ulong READ_TIMER(void)
+{
+ s5pc1xx_timers_t *const timers = (s5pc1xx_timers_t *)S5P_TIMER_BASE;
+
+ return timers->TCNTO4;
+}
+
+int interrupt_init(void)
+{
+ s5pc1xx_timers_t *const timers = (s5pc1xx_timers_t *)S5P_TIMER_BASE;
+
+ /*
+ * @ PWM Timer 4
+ * Timer Freq(HZ) =
+ * PCLK / { (prescaler_value + 1) * (divider_value) }
+ */
+
+ /* set prescaler : 16 */
+ /* set divider : 2 */
+ timers->TCFG0 = (PRESCALER_0 & 0xff) << 8;
+ timers->TCFG1 = (MUX4_DIV_12 & 0xf) << 16;
+
+ if (count_value == 0) {
+
+ /* reset initial value */
+ /* count_value = 2085937.5(HZ) (per 1 sec)*/
+ count_value = get_PCLK() / ((PRESCALER_0 + 1) *
+ (MUX4_DIV_12 + 1));
+
+ /* count_value / 100 = 20859.375(HZ) (per 10 msec) */
+ count_value = count_value / 100;
+ }
+
+ /* set count value */
+ timers->TCNTB4 = count_value;
+ lastdec = count_value;
+
+ /* auto reload & manual update */
+ timers->TCON = (timers->TCON & ~(0x03 << 20)) |
+ S5P_TCON4_AUTO_RELOAD | S5P_TCON4_UPDATE;
+
+ /* start PWM timer 4 */
+ timers->TCON = (timers->TCON & ~(0x03 << 20)) |
+ S5P_TCON4_AUTO_RELOAD | S5P_TCON4_ON;
+
+ timestamp = 0;
+
+ return 0;
+}
+
+
+/*
+ * timer without interrupts
+ */
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+ timestamp = t;
+}
+
+
+/* delay x useconds */
+void udelay(unsigned long usec)
+{
+ ulong tmo, tmp;
+
+ if (usec >= 1000) {
+
+ /*
+ * if "big" number, spread normalization
+ * to seconds
+ * 1. start to normalize for usec to ticks per sec
+ * 2. find number of "ticks" to wait to achieve target
+ * 3. finish normalize.
+ */
+ tmo = usec / 1000;
+ tmo *= CONFIG_SYS_HZ;
+ tmo /= 1000;
+
+ } else {
+ /* else small number, don't kill it prior to HZ multiply */
+ tmo = usec * CONFIG_SYS_HZ;
+ tmo /= (1000 * 1000);
+
+ }
+
+ /* get current timestamp */
+ tmp = get_timer(0);
+
+ if ((tmo + tmp + 1) < tmp) {
+
+ /* if setting this fordward will roll time stamp */
+ /* reset "advancing" timestamp to 0, set lastdec value */
+ reset_timer_masked();
+
+ } else {
+
+ /* else, set advancing stamp wake up time */
+ tmo += tmp;
+ }
+
+ /* loop till event */
+ while (get_timer_masked() < tmo)
+ ; /* nop */
+}
+
+void reset_timer_masked(void)
+{
+ /* reset time */
+ lastdec = READ_TIMER();
+ timestamp = 0;
+}
+
+ulong get_timer_masked(void)
+{
+ /* current tick value */
+ ulong now = READ_TIMER();
+
+ if (lastdec >= now) {
+ /* normal mode */
+ timestamp += lastdec - now;
+
+ } else {
+ /* overflow */
+ timestamp += lastdec + count_value - now;
+
+ }
+ lastdec = now;
+
+ return timestamp;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ /* We overrun in 100s */
+ return CONFIG_SYS_HZ * 100;
+}
+
diff --git a/cpu/arm_cortexa8/s5pc100/speed.c b/cpu/arm_cortexa8/s5pc100/speed.c
new file mode 100644
index 0000000..9b5863b
--- /dev/null
+++ b/cpu/arm_cortexa8/s5pc100/speed.c
@@ -0,0 +1,159 @@
+/*
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, d.mueller at elsoft.ch
+ *
+ * (C) Copyright 2009
+ * Inki Dae, SAMSUNG Electronics, <inki.dae at samsung.com>
+ * Heungjun Kim, SAMSUNG Electronics, <riverful.kim at samsung.com>
+ * Minkyu Kang, SAMSUNG Electronics, <mk7.kang at samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This code should work for both the S3C2400 and the S3C2410
+ * as they seem to have the same PLL and clock machinery inside.
+ * The different address mapping is handled by the s3c24xx.h files below.
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+
+#define APLL 0
+#define MPLL 1
+#define EPLL 2
+#define HPLL 3
+
+/* ------------------------------------------------------------------------- */
+/*
+ * NOTE: This describes the proper use of this file.
+ *
+ * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
+ *
+ * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
+ * the specified bus in HZ.
+ */
+/* ------------------------------------------------------------------------- */
+
+static unsigned long get_PLLCLK(int pllreg)
+{
+ unsigned long r, m, p, s, mask;
+
+ switch (pllreg) {
+ case APLL:
+ r = S5P_APLL_CON_REG;
+ break;
+ case MPLL:
+ r = S5P_MPLL_CON_REG;
+ break;
+ case EPLL:
+ r = S5P_EPLL_CON_REG;
+ break;
+ case HPLL:
+ r = S5P_HPLL_CON_REG;
+ break;
+ default:
+ hang();
+ }
+
+ if (pllreg == APLL)
+ mask = 0x3ff;
+ else
+ mask = 0x1ff;
+
+ m = (r >> 16) & mask;
+ p = (r >> 8) & 0x3f;
+ s = r & 0x7;
+
+ return m * (CONFIG_SYS_CLK_FREQ / (p * (1 << s)));
+}
+
+/* return ARMCORE frequency */
+unsigned long get_ARMCLK(void)
+{
+ unsigned long div, ret;
+
+ div = S5P_CLK_DIV0_REG;
+
+ /* arm_ratio : [6:4] */
+ return get_PLLCLK(APLL) / ((((div >> 4) & 0x7) + 1) * (div & 0x1) + 1);
+}
+
+/* return FCLK frequency */
+unsigned long get_FCLK(void)
+{
+ return get_PLLCLK(APLL);
+}
+
+/* return MCLK frequency */
+unsigned long get_MCLK(void)
+{
+ return get_PLLCLK(MPLL);
+}
+
+/* return HCLK frequency */
+unsigned long get_HCLK(void)
+{
+ unsigned long fclk;
+
+ uint div, div_apll, div_arm, div_d0_bus;
+
+ div = S5P_CLK_DIV0_REG;
+
+ div_apll = (div & 0x1) + 1;
+ div_arm = ((div >> 4) & 0x7) + 1;
+ div_d0_bus = ((div >> 8) & 0x7) + 1;
+
+ fclk = get_FCLK();
+
+ return fclk / (div_apll * div_arm * div_d0_bus);
+}
+
+/* return PCLK frequency */
+unsigned long get_PCLK(void)
+{
+ unsigned long fclk;
+ uint div = S5P_CLK_DIV1_REG;
+ uint div_d1_bus = ((div >> 12) & 0x7) + 1;
+ uint div_pclk = ((div >> 16) & 0x7) + 1;
+
+ /* ASYNC Mode */
+ fclk = get_PLLCLK(MPLL);
+
+ return fclk/(div_d1_bus * div_pclk);
+}
+
+/* return UCLK frequency */
+unsigned long get_UCLK(void)
+{
+ return get_PLLCLK(EPLL);
+}
+
+int print_cpuinfo(void)
+{
+ printf("CPU:\tS5PC100@%luMHz\n", get_ARMCLK() / 1000000);
+ printf("\tFclk = %luMHz, Hclk = %luMHz, Pclk = %luMHz\n",
+ get_FCLK() / 1000000, get_HCLK() / 1000000,
+ get_PCLK() / 1000000);
+
+ return 0;
+}
--
1.5.6.3
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