[U-Boot] [PATCH 3/4] mxc_spi: change to use version config instead of soc config in mxc_spi

[Terry Lv]

In mxc_spi, we used to use soc config, e.g. CONFIG_MX35, CONFIG_MX51.
In this way, we can't exlain the difference of spi in each soc and we
need to modify the driver for each new soc.
Thus, now it use spi version config which can be found in  reference
manual to diff. And new soc just need to add spi version config in
config files to enable it. it would be eaiser than before.

Signed-off-by: Terry Lv <r65388 at freescale.com>
---
 README                |    4 ++-
 drivers/spi/mxc_spi.c |   59 ++++++++++++++++++++++++-------------------------
 2 files changed, 32 insertions(+), 31 deletions(-)
 mode change 100644 => 100755 drivers/spi/mxc_spi.c

diff --git a/README b/README
index 07f1d11..19268d9 100644
--- a/README
+++ b/README
@@ -1910,7 +1910,9 @@ The following options need to be configured:
 		CONFIG_MXC_SPI
 
 		Enables the driver for the SPI controllers on i.MX and MXC
-		SoCs. Currently i.MX31/35/51 are supported.
+		SoCs. The board must also define the version of SPI controller
+		and SPI base addresses that will be used.
+		Currently i.MX31/35/51/53 are supported.
 
 - FPGA Support: CONFIG_FPGA
 
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
old mode 100644
new mode 100755
index 2fa7486..2f48483
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -27,14 +27,12 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
 
-#ifdef CONFIG_MX27
-/* i.MX27 has a completely wrong register layout and register definitions in the
- * datasheet, the correct one is in the Freescale's Linux driver */
+#if defined(CONFIG_SPI_VER_0_4) || defined(CONFIG_SPI_VER_0_0)
 
-#error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
+#error "CSPI version not supported due to drastic differences in register definitions" \
 "See linux mxc_spi driver from Freescale for details."
 
-#elif defined(CONFIG_MX31)
+#elif defined(CONFIG_SPI_VER_0_5)
 
 #define MXC_CSPICTRL_EN		(1 << 0)
 #define MXC_CSPICTRL_MODE	(1 << 1)
@@ -54,13 +52,7 @@
 #define MXC_CSPIPERIOD_32KHZ	(1 << 15)
 #define MAX_SPI_BYTES	4
 
-static unsigned long spi_bases[] = {
-	0x43fa4000,
-	0x50010000,
-	0x53f84000,
-};
-
-#elif defined(CONFIG_MX51)
+#elif defined(CONFIG_SPI_VER_2_3)
 
 #define MXC_CSPICTRL_EN		(1 << 0)
 #define MXC_CSPICTRL_MODE	(1 << 1)
@@ -85,13 +77,7 @@ static unsigned long spi_bases[] = {
 #define MXC_CSPICON_PHA		0
 #define MXC_CSPICON_SSPOL	12
 
-static unsigned long spi_bases[] = {
-	CSPI1_BASE_ADDR,
-	CSPI2_BASE_ADDR,
-	CSPI3_BASE_ADDR,
-};
-
-#elif defined(CONFIG_MX35)
+#elif defined(CONFIG_SPI_VER_0_7)
 
 #define MXC_CSPICTRL_EN		(1 << 0)
 #define MXC_CSPICTRL_MODE	(1 << 1)
@@ -111,15 +97,28 @@ static unsigned long spi_bases[] = {
 #define MXC_CSPIPERIOD_32KHZ	(1 << 15)
 #define MAX_SPI_BYTES	4
 
-static unsigned long spi_bases[] = {
-	0x43fa4000,
-	0x50010000,
-};
-
 #else
-#error "Unsupported architecture"
+#error "Unsupported cspi version"
 #endif
 
+static unsigned long spi_bases[] = {
+#ifdef CONFIG_CSPI1_BASE_ADDR
+	CONFIG_CSPI1_BASE_ADDR,
+#endif
+#ifdef CONFIG_CSPI2_BASE_ADDR
+	CONFIG_CSPI2_BASE_ADDR,
+#endif
+#ifdef CONFIG_CSPI3_BASE_ADDR
+	CONFIG_CSPI3_BASE_ADDR,
+#endif
+#ifdef CONFIG_CSPI4_BASE_ADDR
+	CONFIG_CSPI4_BASE_ADDR,
+#endif
+#ifdef CONFIG_CSPI5_BASE_ADDR
+	CONFIG_CSPI5_BASE_ADDR,
+#endif
+};
+
 #define OUT	MXC_GPIO_DIRECTION_OUT
 
 #define reg_read readl
@@ -129,7 +128,7 @@ struct mxc_spi_slave {
 	struct spi_slave slave;
 	unsigned long	base;
 	u32		ctrl_reg;
-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SPI_VER_2_3)
 	u32		cfg_reg;
 #endif
 	int		gpio;
@@ -167,7 +166,7 @@ u32 get_cspi_div(u32 div)
 	return i;
 }
 
-#if defined(CONFIG_MX31) || defined(CONFIG_MX35)
+#if defined(CONFIG_SPI_VER_0_5) || defined(CONFIG_SPI_VER_0_7)
 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
 		unsigned int max_hz, unsigned int mode)
 {
@@ -187,7 +186,7 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
 		MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
 		MXC_CSPICTRL_DATARATE(div) |
 		MXC_CSPICTRL_EN |
-#ifdef CONFIG_MX35
+#ifdef CONFIG_SPI_VER_0_7
 		MXC_CSPICTRL_SSCTL |
 #endif
 		MXC_CSPICTRL_MODE;
@@ -204,7 +203,7 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
 }
 #endif
 
-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SPI_VER_2_3)
 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
 		unsigned int max_hz, unsigned int mode)
 {
@@ -316,7 +315,7 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
 		MXC_CSPICTRL_BITCOUNT(bitlen - 1);
 
 	reg_write(&regs->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
-#ifdef CONFIG_MX51
+#ifdef CONFIG_SPI_VER_2_3
 	reg_write(&regs->cfg, mxcs->cfg_reg);
 #endif
 
-- 
1.7.0.4