[U-Boot] [PATCH 4/4 v5] Preventing needless switching on and off PLL bypass mode, allowing allow single-stepping through the SPL

[Robert at domain.unknown]

From: Robert Delien <robert at delien.nl>

This patch prevents the needless switching on and off of PLL bypass
mode. With this patch in place, single-stepping through the SPL is
now possible.

Signed-off-by: Robert Delien <robert at delien.nl>
---
 arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c   |    4 ----
 arch/arm/cpu/arm926ejs/mx28/spl_power_init.c |   24 ------------------------
 2 files changed, 0 insertions(+), 28 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
index f2fab7c..cf4361c 100644
--- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
@@ -121,10 +121,6 @@ void mx28_mem_setup_cpu_and_hbus(void)
 	writeb(19 & CLKCTRL_FRAC_FRAC_MASK,
 		(uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]);
 
-	/* Set CPU bypass */
-	writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
-		&clkctrl_regs->hw_clkctrl_clkseq_set);
-
 	/* HBUS = 151MHz */
 	writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set);
 	writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK,
diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
index 271da8d..b3723fc 100644
--- a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
+++ b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
@@ -30,28 +30,6 @@
 
 #include "mx28_init.h"
 
-void mx28_power_clock2xtal(void)
-{
-	struct mx28_clkctrl_regs *clkctrl_regs =
-		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
-
-	/* Set XTAL as CPU reference clock */
-	writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
-		&clkctrl_regs->hw_clkctrl_clkseq_set);
-}
-
-void mx28_power_clock2pll(void)
-{
-	struct mx28_clkctrl_regs *clkctrl_regs =
-		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
-
-	writel(CLKCTRL_PLL0CTRL0_POWER,
-		&clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
-	early_delay(100);
-	writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
-		&clkctrl_regs->hw_clkctrl_clkseq_clr);
-}
-
 void mx28_power_clear_auto_restart(void)
 {
 	struct mx28_rtc_regs *rtc_regs =
@@ -606,7 +584,6 @@ void mx28_power_configure_power_source(void)
 	mx28_src_power_init();
 
 	mx28_5v_boot();
-	mx28_power_clock2pll();
 
 	mx28_init_batt_bo();
 	mx28_switch_vddd_to_dcdc_source();
@@ -888,7 +865,6 @@ void mx28_power_init(void)
 	struct mx28_power_regs *power_regs =
 		(struct mx28_power_regs *)MXS_POWER_BASE;
 
-	mx28_power_clock2xtal();
 	mx28_power_clear_auto_restart();
 	mx28_power_set_linreg();
 	mx28_power_setup_5v_detect();
-- 
1.7.0.4