[U-Boot] [PATCH v3 2/3] Add TI816X support

Andrew Dyer amdyer at gmail.com
Fri Apr 12 17:22:05 CEST 2013


On Fri, Apr 12, 2013 at 7:10 AM, TENART Antoine <atenart at adeneo-embedded.com
> wrote:

> Signed-off-by: Antoine Tenart <atenart at adeneo-embedded.com>
> ---
>  arch/arm/include/asm/arch-am33xx/clock.h           |    4 +
>  arch/arm/include/asm/arch-am33xx/clocks_ti816x.h   |  136 ++++++++
>  arch/arm/include/asm/arch-am33xx/cpu.h             |    4 +
>  arch/arm/include/asm/arch-am33xx/cpu_ti816x.h      |  194 +++++++++++
>  arch/arm/include/asm/arch-am33xx/ddr_defs.h        |    4 +
>  arch/arm/include/asm/arch-am33xx/ddr_defs_ti816x.h |  248 +++++++++++++
>  arch/arm/include/asm/arch-am33xx/hardware.h        |    7 +-
>  arch/arm/include/asm/arch-am33xx/hardware_am33xx.h |    5 +
>  arch/arm/include/asm/arch-am33xx/hardware_ti814x.h |    5 +
>  arch/arm/include/asm/arch-am33xx/hardware_ti816x.h |   56 +++
>  arch/arm/include/asm/arch-am33xx/mmc_host_def.h    |    2 +
>  arch/arm/include/asm/arch-am33xx/mux.h             |    2 +
>  arch/arm/include/asm/arch-am33xx/mux_ti816x.h      |  363
> ++++++++++++++++++++
>  13 files changed, 1025 insertions(+), 5 deletions(-)
>  create mode 100644 arch/arm/include/asm/arch-am33xx/clocks_ti816x.h
>  create mode 100644 arch/arm/include/asm/arch-am33xx/cpu_ti816x.h
>  create mode 100644 arch/arm/include/asm/arch-am33xx/ddr_defs_ti816x.h
>  create mode 100644 arch/arm/include/asm/arch-am33xx/hardware_ti816x.h
>  create mode 100644 arch/arm/include/asm/arch-am33xx/mux_ti816x.h
>
> diff --git a/arch/arm/include/asm/arch-am33xx/clock.h
> b/arch/arm/include/asm/arch-am33xx/clock.h
> index ecb5901..123cc61 100644
> --- a/arch/arm/include/asm/arch-am33xx/clock.h
> +++ b/arch/arm/include/asm/arch-am33xx/clock.h
> @@ -19,6 +19,10 @@
>  #ifndef _CLOCKS_H_
>  #define _CLOCKS_H_
>
> +#if defined(CONFIG_TI816X)
> +#include <asm/arch/clocks_ti816x.h>
> +#else
>  #include <asm/arch/clocks_am33xx.h>
> +#endif
>
>  #endif
> diff --git a/arch/arm/include/asm/arch-am33xx/clocks_ti816x.h
> b/arch/arm/include/asm/arch-am33xx/clocks_ti816x.h
> new file mode 100644
> index 0000000..403db33
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-am33xx/clocks_ti816x.h
> @@ -0,0 +1,136 @@
> +/*
> + * clocks_ti816x.h
> + *
> + * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
> + * Antoine Tenart, <atenart at adeneo-embedded.com>
> + *
> + * Based on TI-PSP-04.00.02.14 :
> + *
> + * (C) Copyright 2006-2008
> + * Texas Instruments, <www.ti.com>
> + * Richard Woodruff <r-woodruff2 at ti.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +#ifndef _CLOCKS_TI816X_H_
> +#define _CLOCKS_TI816X_H_
> +
> +/*
> + * Values supported 400,531,675,796
> + *
> + * On TI8168 rev C, use 400 or 531 MHz !
>

Why?  Is it specific to the EVM or is it general for all rev. C parts.  A
pointer to an errata would be good


> + */
> +#define DDR_PLL_400
>

DDR PLL setup is related to the type of memory used on a particular board.
Seems like it should be set in the board config


> +
> +/* Main PLL */
> +#define MAIN_N                 64
> +#define MAIN_P                 0x1
> +#define MAIN_INTFREQ1          0x8
> +#define MAIN_FRACFREQ1         0x800000
> +#define MAIN_MDIV1             0x2
> +#define MAIN_INTFREQ2          0xE
> +#define MAIN_FRACFREQ2         0x0
> +#define MAIN_MDIV2             0x1
> +#define MAIN_INTFREQ3          0x8
> +#define MAIN_FRACFREQ3         0xAAAAB0
> +#define MAIN_MDIV3             0x3
> +#define MAIN_INTFREQ4          0x9
> +#define MAIN_FRACFREQ4         0x55554F
> +#define MAIN_MDIV4             0x3
> +#define MAIN_INTFREQ5          0x9
> +#define MAIN_FRACFREQ5         0x374BC6
> +#define MAIN_MDIV5             0xC
> +#define MAIN_MDIV6             0x48
> +#define MAIN_MDIV7             0x4
> +
> +/* DDR PLL */
> +/* For 400 MHz */
> +#if defined(DDR_PLL_400)
> +#define DDR_N                  59
> +#define DDR_P                  0x1
> +#define DDR_MDIV1              0x4
> +#define DDR_INTFREQ2           0x8
> +#define DDR_FRACFREQ2          0xD99999
> +#define DDR_MDIV2              0x1E
> +#define DDR_INTFREQ3           0x8
> +#define DDR_FRACFREQ3          0x0
> +#define DDR_MDIV3              0x4
> +#define DDR_INTFREQ4           0xE /* Expansion DDR clk */
> +#define DDR_FRACFREQ4          0x0
> +#define DDR_MDIV4              0x4
> +#define DDR_INTFREQ5           0xE /* Expansion DDR clk */
> +#define DDR_FRACFREQ5          0x0
> +#define DDR_MDIV5              0x4
> +#endif
> +
> +/* For 531 MHz */
> +#if defined(DDR_PLL_531)
> +#define DDR_N                  59
> +#define DDR_P                  0x1
> +#define DDR_MDIV1              0x3
> +#define DDR_INTFREQ2           0x8
> +#define DDR_FRACFREQ2          0xD99999
> +#define DDR_MDIV2              0x1E
> +#define DDR_INTFREQ3           0x8
> +#define DDR_FRACFREQ3          0x0
> +#define DDR_MDIV3              0x4
> +#define DDR_INTFREQ4           0xE /* Expansion DDR clk */
> +#define DDR_FRACFREQ4          0x0
> +#define DDR_MDIV4              0x4
> +#define DDR_INTFREQ5           0xE /* Expansion DDR clk */
> +#define DDR_FRACFREQ5          0x0
> +#define DDR_MDIV5              0x4
> +#endif
> +
> +/* For 675 MHz */
> +#if defined(DDR_PLL_675)
> +#define DDR_N                  50
> +#define DDR_P                  0x1
> +#define DDR_MDIV1              0x2
> +#define DDR_INTFREQ2           0x9
> +#define DDR_FRACFREQ2          0x0
> +#define DDR_MDIV2              0x19
> +#define DDR_INTFREQ3           0x13
> +#define DDR_FRACFREQ3          0x800000
> +#define DDR_MDIV3              0x2
> +#define DDR_INTFREQ4           0xE /* Expansion DDR clk */
> +#define DDR_FRACFREQ4          0x0
> +#define DDR_MDIV4              0x4
> +#define DDR_INTFREQ5           0xE /* Expansion DDR clk */
> +#define DDR_FRACFREQ5          0x0
> +#define DDR_MDIV5              0x4
> +#endif
> +
> +/* For 796 MHz */
> +#if defined(DDR_PLL_796)
> +#define DDR_N                  59
> +#define DDR_P                  0x1
> +#define DDR_MDIV1              0x2
> +#define DDR_INTFREQ2           0x8
> +#define DDR_FRACFREQ2          0xD99999
> +#define DDR_MDIV2              0x1E
> +#define DDR_INTFREQ3           0x8
> +#define DDR_FRACFREQ3          0x0
> +#define DDR_MDIV3              0x4
> +#define DDR_INTFREQ4           0xE /* Expansion DDR clk */
> +#define DDR_FRACFREQ4          0x0
> +#define DDR_MDIV4              0x4
> +#define DDR_INTFREQ5           0xE /* Expansion DDR clk */
> +#define DDR_FRACFREQ5          0x0
> +#define DDR_MDIV5              0x4
> +#endif
> +
> +#endif /* endif _CLOCKS_TI816X_H_ */
> diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h
> b/arch/arm/include/asm/arch-am33xx/cpu.h
> index 13c0667..34b3aa9 100644
> --- a/arch/arm/include/asm/arch-am33xx/cpu.h
> +++ b/arch/arm/include/asm/arch-am33xx/cpu.h
> @@ -25,6 +25,10 @@
>
>  #include <asm/arch/hardware.h>
>
> +#if defined(CONFIG_TI816X)
> +#include <asm/arch/cpu_ti816x.h>
> +#endif
> +
>  #define BIT(x)                         (1 << x)
>  #define CL_BIT(x)                      (0 << x)
>
> diff --git a/arch/arm/include/asm/arch-am33xx/cpu_ti816x.h
> b/arch/arm/include/asm/arch-am33xx/cpu_ti816x.h
> new file mode 100644
> index 0000000..515dba4
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-am33xx/cpu_ti816x.h
> @@ -0,0 +1,194 @@
> +/*
> + * cpu_ti816x.h
> + *
> + * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
> + * Antoine Tenart, <atenart at adeneo-embedded.com>
> + *
> + * Based on TI-PSP-04.00.02.14 :
> + *
> + * (C) Copyright 2006
> + * Texas Instruments, <www.ti.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + *
> + */
> +
> +#ifndef _TI816X_CPU_H
> +#define _TI816X_CPU_H
> +
> +#include <asm/arch/hardware.h>
> +
> +/* Control */
> +#define CONTROL_STATUS         (CTRL_BASE + 0x40)
> +
> +/* PLL related registers */
> +#define MAINPLL_CTRL           (CTRL_BASE + 0x0400)
> +#define MAINPLL_PWD            (CTRL_BASE + 0x0404)
> +#define MAINPLL_FREQ1          (CTRL_BASE + 0x0408)
> +#define MAINPLL_DIV1           (CTRL_BASE + 0x040C)
> +#define MAINPLL_FREQ2          (CTRL_BASE + 0x0410)
> +#define MAINPLL_DIV2           (CTRL_BASE + 0x0414)
> +#define MAINPLL_FREQ3          (CTRL_BASE + 0x0418)
> +#define MAINPLL_DIV3           (CTRL_BASE + 0x041C)
> +#define MAINPLL_FREQ4          (CTRL_BASE + 0x0420)
> +#define MAINPLL_DIV4           (CTRL_BASE + 0x0424)
> +#define MAINPLL_FREQ5          (CTRL_BASE + 0x0428)
> +#define MAINPLL_DIV5           (CTRL_BASE + 0x042C)
> +#define MAINPLL_DIV6           (CTRL_BASE + 0x0434)
> +#define MAINPLL_DIV7           (CTRL_BASE + 0x043C)
> +
> +#define DDRPLL_CTRL            (CTRL_BASE + 0x0440)
> +#define DDRPLL_PWD             (CTRL_BASE + 0x0444)
> +#define DDRPLL_DIV1            (CTRL_BASE + 0x044C)
> +#define DDRPLL_FREQ2           (CTRL_BASE + 0x0450)
> +#define DDRPLL_DIV2            (CTRL_BASE + 0x0454)
> +#define DDRPLL_FREQ3           (CTRL_BASE + 0x0458)
> +#define DDRPLL_DIV3            (CTRL_BASE + 0x045C)
> +#define DDRPLL_FREQ4           (CTRL_BASE + 0x0460)
> +#define DDRPLL_DIV4            (CTRL_BASE + 0x0464)
> +#define DDRPLL_FREQ5           (CTRL_BASE + 0x0468)
> +#define DDRPLL_DIV5            (CTRL_BASE + 0x046C)
> +
> +#define DDR_RCD                        (CTRL_BASE + 0x070C)
> +
> +/* PRCM */
> +#define CM_DPLL_OFFSET         (PRCM_BASE + 0x0300)
> +
> +#ifdef CONFIG_TI816X
> +#define CM_TIMER1_CLKSEL       (CM_DPLL_OFFSET + 0x90)
> +
> +/* Timers */
> +#define CM_ALWON_TIMER_0_CLKCTRL       (PRCM_BASE + 0x156C)
> +#define CM_ALWON_TIMER_1_CLKCTRL       (PRCM_BASE + 0x1570)
> +#define CM_ALWON_TIMER_2_CLKCTRL       (PRCM_BASE + 0x1574)
> +#define CM_ALWON_TIMER_3_CLKCTRL       (PRCM_BASE + 0x1578)
> +#define CM_ALWON_TIMER_4_CLKCTRL       (PRCM_BASE + 0x157C)
> +#define CM_ALWON_TIMER_5_CLKCTRL       (PRCM_BASE + 0x1580)
> +#define CM_ALWON_TIMER_6_CLKCTRL       (PRCM_BASE + 0x1584)
> +#define CM_ALWON_TIMER_7_CLKCTRL       (PRCM_BASE + 0x1588)
> +#endif
> +
> +#define CM_ALWON_WDTIMER_CLKCTRL       (PRCM_BASE + 0x158C)
> +#define CM_ALWON_SPI_CLKCTRL           (PRCM_BASE + 0x1590)
> +#define CM_ALWON_CONTROL_CLKCTRL       (PRCM_BASE + 0x15C4)
> +
> +#define CM_ALWON_L3_SLOW_CLKSTCTRL     (PRCM_BASE + 0x1400)
> +
> +#ifdef CONFIG_TI816X
> +#define CM_ALWON_CUST_EFUSE_CLKCTRL    (PRCM_BASE + 0x1628)
> +#endif
> +
> +#define CM_ALWON_GPIO_0_CLKCTRL                (PRCM_BASE + 0x155c)
> +#define CM_ALWON_GPIO_0_OPTFCLKEN_DBCLK (PRCM_BASE + 0x155c)
> +
> +#define CM_ALWON_GPIO_1_CLKCTRL                (PRCM_BASE + 0x1560)
> +/* Ethernet */
> +#define CM_ETHERNET_CLKSTCTRL          (PRCM_BASE + 0x1404)
> +#define CM_ALWON_ETHERNET_0_CLKCTRL    (PRCM_BASE + 0x15D4)
> +#define CM_ALWON_ETHERNET_1_CLKCTRL    (PRCM_BASE + 0x15D8)
> +
> +/* UARTs */
> +#define CM_ALWON_UART_0_CLKCTRL                (PRCM_BASE + 0x1550)
> +#define CM_ALWON_UART_1_CLKCTRL                (PRCM_BASE + 0x1554)
> +#define CM_ALWON_UART_2_CLKCTRL                (PRCM_BASE + 0x1558)
> +
> +/* I2C */
> +/* Note: In ti814x I2C0 and I2C2 have common clk control */
> +#define CM_ALWON_I2C_0_CLKCTRL         (PRCM_BASE + 0x1564)
> +
> +/* HSMMC */
> +#ifdef CONFIG_TI816X
> +#define CM_ALWON_HSMMC_CLKCTRL         (PRCM_BASE + 0x15B0)
> +#endif
> +
> +/*DMM & EMIF4 MMR Declaration*/
> +
> +/* 0x420 = 0x460 - the lisa registers offset from the DMM region */
> +#define DMM_PAT_BASE_ADDR              (DMM_BASE + 0x420)
> +
> +#define EMIF4_0_SDRAM_ZQCR             (EMIF4_0_CFG_BASE + 0xC8)
> +#define EMIF4_0_SDRAM_CONFIG           (EMIF4_0_CFG_BASE + 0x08)
> +#define EMIF4_0_SDRAM_CONFIG2          (EMIF4_0_CFG_BASE + 0x0C)
> +#define EMIF4_0_SDRAM_REF_CTRL         (EMIF4_0_CFG_BASE + 0x10)
> +#define EMIF4_0_SDRAM_REF_CTRL_SHADOW  (EMIF4_0_CFG_BASE + 0x14)
> +#define EMIF4_0_SDRAM_TIM_1            (EMIF4_0_CFG_BASE + 0x18)
> +#define EMIF4_0_SDRAM_TIM_1_SHADOW     (EMIF4_0_CFG_BASE + 0x1C)
> +#define EMIF4_0_SDRAM_TIM_2            (EMIF4_0_CFG_BASE + 0x20)
> +#define EMIF4_0_SDRAM_TIM_2_SHADOW     (EMIF4_0_CFG_BASE + 0x24)
> +#define EMIF4_0_SDRAM_TIM_3            (EMIF4_0_CFG_BASE + 0x28)
> +#define EMIF4_0_SDRAM_TIM_3_SHADOW     (EMIF4_0_CFG_BASE + 0x2C)
> +#define EMIF4_0_DDR_PHY_CTRL_1         (EMIF4_0_CFG_BASE + 0xE4)
> +#define EMIF4_0_DDR_PHY_CTRL_1_SHADOW  (EMIF4_0_CFG_BASE + 0xE8)
> +#define EMIF4_0_IODFT_TLGC             (EMIF4_0_CFG_BASE + 0x60)
> +
> +#define EMIF4_1_SDRAM_ZQCR             (EMIF4_1_CFG_BASE + 0xC8)
> +#define EMIF4_1_SDRAM_CONFIG           (EMIF4_1_CFG_BASE + 0x08)
> +#define EMIF4_1_SDRAM_CONFIG2          (EMIF4_1_CFG_BASE + 0x0C)
> +#define EMIF4_1_SDRAM_REF_CTRL         (EMIF4_1_CFG_BASE + 0x10)
> +#define EMIF4_1_SDRAM_REF_CTRL_SHADOW  (EMIF4_1_CFG_BASE + 0x14)
> +#define EMIF4_1_SDRAM_TIM_1            (EMIF4_1_CFG_BASE + 0x18)
> +#define EMIF4_1_SDRAM_TIM_1_SHADOW     (EMIF4_1_CFG_BASE + 0x1C)
> +#define EMIF4_1_SDRAM_TIM_2            (EMIF4_1_CFG_BASE + 0x20)
> +#define EMIF4_1_SDRAM_TIM_2_SHADOW     (EMIF4_1_CFG_BASE + 0x24)
> +#define EMIF4_1_SDRAM_TIM_3            (EMIF4_1_CFG_BASE + 0x28)
> +#define EMIF4_1_SDRAM_TIM_3_SHADOW     (EMIF4_1_CFG_BASE + 0x2C)
> +#define EMIF4_1_DDR_PHY_CTRL_1         (EMIF4_1_CFG_BASE + 0xE4)
> +#define EMIF4_1_DDR_PHY_CTRL_1_SHADOW  (EMIF4_1_CFG_BASE + 0xE8)
> +#define EMIF4_1_IODFT_TLGC             (EMIF4_1_CFG_BASE + 0x60)
> +
> +/*EMIF4 PRCM Defintion*/
> +#define CM_DEFAULT_L3_FAST_CLKSTCTRL   (PRCM_BASE + 0x0508)
> +#define CM_DEFAULT_EMIF_0_CLKCTRL      (PRCM_BASE + 0x0520)
> +#define CM_DEFAULT_EMIF_1_CLKCTRL      (PRCM_BASE + 0x0524)
> +#define CM_DEFAULT_DMM_CLKCTRL         (PRCM_BASE + 0x0528)
> +#define CM_DEFAULT_FW_CLKCTRL          (PRCM_BASE + 0x052C)
> +
> +/* GPMC related */
> +#define GPMC_CONFIG_CS0                (0x60)
> +#define GPMC_CONFIG_CS0_BAS    (GPMC_BASE + GPMC_CONFIG_CS0)
> +#define GPMC_CONFIG1           (0x00)
> +#define GPMC_CONFIG2           (0x04)
> +#define GPMC_CONFIG3           (0x08)
> +#define GPMC_CONFIG4           (0x0C)
> +#define GPMC_CONFIG5           (0x10)
> +#define GPMC_CONFIG6           (0x14)
> +#define GPMC_CONFIG7           (0x18)
> +
> +/* WDT related */
> +#define WDT_WDSC               (WDT_BASE + 0x010)
> +#define WDT_WDST               (WDT_BASE + 0x014)
> +#define WDT_WISR               (WDT_BASE + 0x018)
> +#define WDT_WIER               (WDT_BASE + 0x01C)
> +#define WDT_WWER               (WDT_BASE + 0x020)
> +#define WDT_WCLR               (WDT_BASE + 0x024)
> +#define WDT_WCRR               (WDT_BASE + 0x028)
> +#define WDT_WLDR               (WDT_BASE + 0x02C)
> +#define WDT_WTGR               (WDT_BASE + 0x030)
> +#define WDT_WWPS               (WDT_BASE + 0x034)
> +#define WDT_WDLY               (WDT_BASE + 0x044)
> +#define WDT_WSPR               (WDT_BASE + 0x048)
> +#define WDT_WIRQEOI            (WDT_BASE + 0x050)
> +#define WDT_WIRQSTATRAW                (WDT_BASE + 0x054)
> +#define WDT_WIRQSTAT           (WDT_BASE + 0x058)
> +#define WDT_WIRQENSET          (WDT_BASE + 0x05C)
> +#define WDT_WIRQENCLR          (WDT_BASE + 0x060)
> +
> +#define WDT_UNFREEZE           (CTRL_BASE + 0x100)
> +
> +#endif /* _TI816X_CPU_H */
> diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
> b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
> index 15ca4c1..b959ba8 100644
> --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
> +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
> @@ -22,6 +22,10 @@
>  #include <asm/arch/hardware.h>
>  #include <asm/emif.h>
>
> +#if defined(CONFIG_TI816X)
> +#include <asm/arch/ddr_defs_ti816x.h>
> +#endif
> +
>  /* AM335X EMIF Register values */
>  #define VTP_CTRL_READY         (0x1 << 5)
>  #define VTP_CTRL_ENABLE                (0x1 << 6)
> diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs_ti816x.h
> b/arch/arm/include/asm/arch-am33xx/ddr_defs_ti816x.h
> new file mode 100644
> index 0000000..4c0fe9d
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs_ti816x.h
> @@ -0,0 +1,248 @@
> +/*
> + * ddr_defs_ti816x.h
> + *
> + * ddr specific header for TI816X
> + *
> + * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
> + * Antoine Tenart, <atenart at adeneo-embedded.com>
> + *
> + * Based on TI-PSP-04.00.02.14 :
> + *
> + * Copyright (C) 2010 Texas Instruments
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> + *
> + */
> +
> +#ifndef _DDR_DEFS_TI816X_H
> +#define _DDR_DEFS_TI816X_H
> +
> +#include <asm/arch/hardware.h>
> +
> +#ifdef CONFIG_TI816X_EVM_DDR3
> +
> +#define CONFIG_TI816X_DDR3_796         /* Values supported
> 400,531,675,796 */
>

Almost everything in this file should be defined on a per board basis, not
in a generic header file.  Also should combine defines with the PLL setup
above so there is no possibility of mismatch between the two



> diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h
> b/arch/arm/include/asm/arch-am33xx/hardware.h
> index 5a27f9c..7f3b555 100644
> --- a/arch/arm/include/asm/arch-am33xx/hardware.h
> +++ b/arch/arm/include/asm/arch-am33xx/hardware.h
> @@ -23,6 +23,8 @@
>  #include <asm/arch/omap.h>
>  #ifdef CONFIG_AM33XX
>  #include <asm/arch/hardware_am33xx.h>
> +#elif defined(CONFIG_TI816X)
> +#include <asm/arch/hardware_ti816x.h>
>  #elif defined(CONFIG_TI814X)
>  #include <asm/arch/hardware_ti814x.h>
>  #endif
> @@ -67,15 +69,10 @@
>  /* DDR Base address */
>  #define DDR_CTRL_ADDR                  0x44E10E04
>  #define DDR_CONTROL_BASE_ADDR          0x44E11404
> -#define DDR_PHY_CMD_ADDR2              0x47C0C800
> -#define DDR_PHY_DATA_ADDR2             0x47C0C8C8
>
>  /* UART */
>  #define DEFAULT_UART_BASE              UART0_BASE
>
> -#define DDRPHY_0_CONFIG_BASE           (CTRL_BASE + 0x1400)
> -#define DDRPHY_CONFIG_BASE             DDRPHY_0_CONFIG_BASE
> -
>  /* GPMC Base address */
>  #define GPMC_BASE                      0x50000000
>
> diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
> b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
> index fa02f19..553c3bd 100644
> --- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
> +++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
> @@ -43,8 +43,13 @@
>  /* DDR Base address */
>  #define DDR_PHY_CMD_ADDR               0x44E12000
>  #define DDR_PHY_DATA_ADDR              0x44E120C8
> +#define DDR_PHY_CMD_ADDR2              0x47C0C800
> +#define DDR_PHY_DATA_ADDR2             0x47C0C8C8
>  #define DDR_DATA_REGS_NR               2
>
> +#define DDRPHY_0_CONFIG_BASE           (CTRL_BASE + 0x1400)
> +#define DDRPHY_CONFIG_BASE             DDRPHY_0_CONFIG_BASE
> +
>  /* CPSW Config space */
>  #define CPSW_MDIO_BASE                 0x4A101000
>
> diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
> b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
> index a950ac3..c075274 100644
> --- a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
> +++ b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
> @@ -42,8 +42,13 @@
>  /* DDR Base address */
>  #define DDR_PHY_CMD_ADDR               0x47C0C400
>  #define DDR_PHY_DATA_ADDR              0x47C0C4C8
> +#define DDR_PHY_CMD_ADDR2              0x47C0C800
> +#define DDR_PHY_DATA_ADDR2             0x47C0C8C8
>  #define DDR_DATA_REGS_NR               4
>
> +#define DDRPHY_0_CONFIG_BASE           (CTRL_BASE + 0x1400)
> +#define DDRPHY_CONFIG_BASE             DDRPHY_0_CONFIG_BASE
> +
>  /* CPSW Config space */
>  #define CPSW_MDIO_BASE                 0x4A100800
>
> diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h
> b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h
> new file mode 100644
> index 0000000..60daf55
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h
> @@ -0,0 +1,56 @@
> +/*
> + * hardware_ti816x.h
> + *
> + * TI816x hardware specific header
> + *
> + * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
> + * Antoine Tenart, <atenart at adeneo-embedded.com>
> + * Based on TI-PSP-04.00.02.14
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __AM33XX_HARDWARE_TI816X_H
> +#define __AM33XX_HARDWARE_TI816X_H
> +
> +/* Watchdog Timer */
> +#define WDT_BASE               0x480C2000
> +
> +/* Control Module Base Address */
> +#define CTRL_BASE              0x48140000
> +
> +/* PRCM Base Address */
> +#define PRCM_BASE              0x48180000
> +
> +/* VTP Base address */
> +#define VTP0_CTRL_ADDR         0x48198358
> +
> +/* DDR Base address */
> +#define DDR_PHY_CMD_ADDR       0x48198000
> +#define DDR_PHY_DATA_ADDR      0x481980C8
> +#define DDR_PHY_CMD_ADDR2      0x4819A000
> +#define DDR_PHY_DATA_ADDR2     0x4819A0C8
> +#define DDR_DATA_REGS_NR       4
> +
> +/* UART */
> +#define UART0_BASE             0x48020000
> +#define UART1_BASE             0x48022000
> +#define UART2_BASE             0x48024000
> +
> +#define DDRPHY_0_CONFIG_BASE   0x48198000
> +#define DDRPHY_1_CONFIG_BASE   0x4819a000
> +#define DDRPHY_CONFIG_BASE     ((emif == 0) ? \
> +       DDRPHY_0_CONFIG_BASE : DDRPHY_1_CONFIG_BASE)
> +
> +/* RTC base address */
> +#define RTC_BASE               0x480C0000
> +
> +#endif /* __AM33XX_HARDWARE_TI816X_H */
> diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
> b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
> index e0a3b8b..09d7a77 100644
> --- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
> +++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
> @@ -155,6 +155,8 @@ typedef struct hsmmc {
>  /* Clock Configurations and Macros */
>  #ifdef CONFIG_AM33XX
>  #define MMC_CLOCK_REFERENCE    96 /* MHz */
> +#elif defined(CONFIG_TI816X)
> +#define MMC_CLOCK_REFERENCE    48 /* MHz */
>  #elif defined(CONFIG_TI814X)
>  #define MMC_CLOCK_REFERENCE    192 /* MHz */
>  #endif
> diff --git a/arch/arm/include/asm/arch-am33xx/mux.h
> b/arch/arm/include/asm/arch-am33xx/mux.h
> index 1c6b65f..4caa4d8 100644
> --- a/arch/arm/include/asm/arch-am33xx/mux.h
> +++ b/arch/arm/include/asm/arch-am33xx/mux.h
> @@ -23,6 +23,8 @@
>  #include <asm/arch/mux_am33xx.h>
>  #elif defined(CONFIG_TI814X)
>  #include <asm/arch/mux_ti814x.h>
> +#elif defined(CONFIG_TI816X)
> +#include <asm/arch/mux_ti816x.h>
>  #endif
>
>  struct module_pin_mux {
> diff --git a/arch/arm/include/asm/arch-am33xx/mux_ti816x.h
> b/arch/arm/include/asm/arch-am33xx/mux_ti816x.h
> new file mode 100644
> index 0000000..0fcd49e
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-am33xx/mux_ti816x.h
> @@ -0,0 +1,363 @@
> +/*
> + * mux_ti816x.h
> + *
> + * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
> + * Antoine Tenart, <atenart at adeneo-embedded.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef _MUX_TI816X_H_
> +#define _MUX_TI816X_H_
> +
> +#include <common.h>
> +#include <asm/io.h>
> +
> +#define MUX_CFG(value, offset)  \
> +       __raw_writel(value, (CTRL_BASE + offset));
> +
> +#define PULLDOWN_EN (0x0 << 4) /* Pull Down Selection */
> +#define PULLUP_EN   (0x1 << 4) /* Pull Up Selection */
> +#define PULLUDEN    (0x0 << 3) /* Pull up enabled */
> +#define PULLUDDIS   (0x1 << 3) /* Pull up disabled */
> +#define MODE(val)              val /* used for Readability */
>

shouldn't this have parenthesis to protect the parameter like so
#define MODE(val) (val)

+
> +
> +/*
> + * PAD CONTROL OFFSETS
> + * Field names corresponds to the pad signal name
> + */
> +struct pad_signals {
> +       int pincntl1;
> +       int pincntl2;
> +       int pincntl3;
> +       int pincntl4;
> +       int pincntl5;
> +       int pincntl6;
> +       int pincntl7;
> +       int pincntl8;
> +       int pincntl9;
> +       int pincntl10;
> +       int pincntl11;
> +       int pincntl12;
> +       int pincntl13;
> +       int pincntl14;
> +       int pincntl15;
> +       int pincntl16;
> +       int pincntl17;
> +       int pincntl18;
> +       int pincntl19;
> +       int pincntl20;
> +       int pincntl21;
> +       int pincntl22;
> +       int pincntl23;
> +       int pincntl24;
> +       int pincntl25;
> +       int pincntl26;
> +       int pincntl27;
> +       int pincntl28;
> +       int pincntl29;
> +       int pincntl30;
> +       int pincntl31;
> +       int pincntl32;
> +       int pincntl33;
> +       int pincntl34;
> +       int pincntl35;
> +       int pincntl36;
> +       int pincntl37;
> +       int pincntl38;
> +       int pincntl39;
> +       int pincntl40;
> +       int pincntl41;
> +       int pincntl42;
> +       int pincntl43;
> +       int pincntl44;
> +       int pincntl45;
> +       int pincntl46;
> +       int pincntl47;
> +       int pincntl48;
> +       int pincntl49;
> +       int pincntl50;
> +       int pincntl51;
> +       int pincntl52;
> +       int pincntl53;
> +       int pincntl54;
> +       int pincntl55;
> +       int pincntl56;
> +       int pincntl57;
> +       int pincntl58;
> +       int pincntl59;
> +       int pincntl60;
> +       int pincntl61;
> +       int pincntl62;
> +       int pincntl63;
> +       int pincntl64;
> +       int pincntl65;
> +       int pincntl66;
> +       int pincntl67;
> +       int pincntl68;
> +       int pincntl69;
> +       int pincntl70;
> +       int pincntl71;
> +       int pincntl72;
> +       int pincntl73;
> +       int pincntl74;
> +       int pincntl75;
> +       int pincntl76;
> +       int pincntl77;
> +       int pincntl78;
> +       int pincntl79;
> +       int pincntl80;
> +       int pincntl81;
> +       int pincntl82;
> +       int pincntl83;
> +       int pincntl84;
> +       int pincntl85;
> +       int pincntl86;
> +       int pincntl87;
> +       int pincntl88;
> +       int pincntl89;
> +       int pincntl90;
> +       int pincntl91;
> +       int pincntl92;
> +       int pincntl93;
> +       int pincntl94;
> +       int pincntl95;
> +       int pincntl96;
> +       int pincntl97;
> +       int pincntl98;
> +       int pincntl99;
> +       int pincntl100;
> +       int pincntl101;
> +       int pincntl102;
> +       int pincntl103;
> +       int pincntl104;
> +       int pincntl105;
> +       int pincntl106;
> +       int pincntl107;
> +       int pincntl108;
> +       int pincntl109;
> +       int pincntl110;
> +       int pincntl111;
> +       int pincntl112;
> +       int pincntl113;
> +       int pincntl114;
> +       int pincntl115;
> +       int pincntl116;
> +       int pincntl117;
> +       int pincntl118;
> +       int pincntl119;
> +       int pincntl120;
> +       int pincntl121;
> +       int pincntl122;
> +       int pincntl123;
> +       int pincntl124;
> +       int pincntl125;
> +       int pincntl126;
> +       int pincntl127;
> +       int pincntl128;
> +       int pincntl129;
> +       int pincntl130;
> +       int pincntl131;
> +       int pincntl132;
> +       int pincntl133;
> +       int pincntl134;
> +       int pincntl135;
> +       int pincntl136;
> +       int pincntl137;
> +       int pincntl138;
> +       int pincntl139;
> +       int pincntl140;
> +       int pincntl141;
> +       int pincntl142;
> +       int pincntl143;
> +       int pincntl144;
> +       int pincntl145;
> +       int pincntl146;
> +       int pincntl147;
> +       int pincntl148;
> +       int pincntl149;
> +       int pincntl150;
> +       int pincntl151;
> +       int pincntl152;
> +       int pincntl153;
> +       int pincntl154;
> +       int pincntl155;
> +       int pincntl156;
> +       int pincntl157;
> +       int pincntl158;
> +       int pincntl159;
> +       int pincntl160;
> +       int pincntl161;
> +       int pincntl162;
> +       int pincntl163;
> +       int pincntl164;
> +       int pincntl165;
> +       int pincntl166;
> +       int pincntl167;
> +       int pincntl168;
> +       int pincntl169;
> +       int pincntl170;
> +       int pincntl171;
> +       int pincntl172;
> +       int pincntl173;
> +       int pincntl174;
> +       int pincntl175;
> +       int pincntl176;
> +       int pincntl177;
> +       int pincntl178;
> +       int pincntl179;
> +       int pincntl180;
> +       int pincntl181;
> +       int pincntl182;
> +       int pincntl183;
> +       int pincntl184;
> +       int pincntl185;
> +       int pincntl186;
> +       int pincntl187;
> +       int pincntl188;
> +       int pincntl189;
> +       int pincntl190;
> +       int pincntl191;
> +       int pincntl192;
> +       int pincntl193;
> +       int pincntl194;
> +       int pincntl195;
> +       int pincntl196;
> +       int pincntl197;
> +       int pincntl198;
> +       int pincntl199;
> +       int pincntl200;
> +       int pincntl201;
> +       int pincntl202;
> +       int pincntl203;
> +       int pincntl204;
> +       int pincntl205;
> +       int pincntl206;
> +       int pincntl207;
> +       int pincntl208;
> +       int pincntl209;
> +       int pincntl210;
> +       int pincntl211;
> +       int pincntl212;
> +       int pincntl213;
> +       int pincntl214;
> +       int pincntl215;
> +       int pincntl216;
> +       int pincntl217;
> +       int pincntl218;
> +       int pincntl219;
> +       int pincntl220;
> +       int pincntl221;
> +       int pincntl222;
> +       int pincntl223;
> +       int pincntl224;
> +       int pincntl225;
> +       int pincntl226;
> +       int pincntl227;
> +       int pincntl228;
> +       int pincntl229;
> +       int pincntl230;
> +       int pincntl231;
> +       int pincntl232;
> +       int pincntl233;
> +       int pincntl234;
> +       int pincntl235;
> +       int pincntl236;
> +       int pincntl237;
> +       int pincntl238;
> +       int pincntl239;
> +       int pincntl240;
> +       int pincntl241;
> +       int pincntl242;
> +       int pincntl243;
> +       int pincntl244;
> +       int pincntl245;
> +       int pincntl246;
> +       int pincntl247;
> +       int pincntl248;
> +       int pincntl249;
> +       int pincntl250;
> +       int pincntl251;
> +       int pincntl252;
> +       int pincntl253;
> +       int pincntl254;
> +       int pincntl255;
> +       int pincntl256;
> +       int pincntl257;
> +       int pincntl258;
> +       int pincntl259;
> +       int pincntl260;
> +       int pincntl261;
> +       int pincntl262;
> +       int pincntl263;
> +       int pincntl264;
> +       int pincntl265;
> +       int pincntl266;
> +       int pincntl267;
> +       int pincntl268;
> +       int pincntl269;
> +       int pincntl270;
> +       int pincntl271;
> +       int pincntl272;
> +       int pincntl273;
> +       int pincntl274;
> +       int pincntl275;
> +       int pincntl276;
> +       int pincntl277;
> +       int pincntl278;
> +       int pincntl279;
> +       int pincntl280;
> +       int pincntl281;
> +       int pincntl282;
> +       int pincntl283;
> +       int pincntl284;
> +       int pincntl285;
> +       int pincntl286;
> +       int pincntl287;
> +       int pincntl288;
> +       int pincntl289;
> +       int pincntl290;
> +       int pincntl291;
> +       int pincntl292;
> +       int pincntl293;
> +       int pincntl294;
> +       int pincntl295;
> +       int pincntl296;
> +       int pincntl297;
> +       int pincntl298;
> +       int pincntl299;
> +       int pincntl300;
> +       int pincntl301;
> +       int pincntl302;
> +       int pincntl303;
> +       int pincntl304;
> +       int pincntl305;
> +       int pincntl306;
> +       int pincntl307;
> +       int pincntl308;
> +       int pincntl309;
> +       int pincntl310;
> +       int pincntl311;
> +       int pincntl312;
> +       int pincntl313;
> +       int pincntl314;
> +       int pincntl315;
> +       int pincntl316;
> +       int pincntl317;
> +       int pincntl318;
> +       int pincntl319;
> +       int pincntl320;
> +       int pincntl321;
> +       int pincntl322;
> +       int pincntl323;
> +};
> +
> +#endif /* endif _MUX_TI816X_H_ */
> --
> 1.7.10.4
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