[U-Boot] [PATCH] Add NanoBone board support

[Tom Rini]

On Tue, Apr 16, 2013 at 04:02:34PM +0100, Mark Jackson wrote:

[snip]
> +static struct emif_regs ddr3_emif_reg_data = {
> +	.sdram_config = MT41J128MJT125_EMIF_SDCFG,
> +	.ref_ctrl = MT41J128MJT125_EMIF_SDREF,
> +	.sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
> +	.sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
> +	.sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
> +	.zq_config = MT41J128MJT125_ZQ_CFG,
> +	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY,

On the READ_LATENCY, you probably want | PHY_EN_DYN_PWRDN for that
(since it's not part of MT41J128MJT125_EMIF_READ_LATENCY) bit of
savings.

> +static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])

Why are we bringing this in?

[snip]
> +	config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
> +		   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);

And are you unable to run at 400MHz here?  Or just weren't aware /
having tried updating the timing parameters, etc?

[snip]
> +static struct cpsw_platform_data cpsw_data = {
> +	.mdio_base		= CPSW_MDIO_BASE,
> +	.cpsw_base		= CPSW_BASE,
> +	.mdio_div		= 0xff,
> +	.channels		= 8,
> +	.cpdma_reg_ofs		= 0x800,
> +	.slaves			= 2,

Is this all that was needed for both interfaces to work in U-Boot, along
with a config change or two?  If so, I should take a stab at getting
both working on the EVM-SK.

[snip]
> +	writel(PORT1_MII_MODE_ENABLE | PORT2_MII_MODE_ENABLE, &cdev->miisel);
> +	cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII;

Can't you just do that in the struct?  And avoid the checkpatch warning
too.

[snip]
> +#define CONFIG_SYS_NO_FLASH

But you have NOR.  Is it not working yet?

> +/*
> + * memtest works on 8 MB in DRAM after skipping 32MB from
> + * start addr of ram disk
> + */
> +#define CONFIG_SYS_MEMTEST_START	(PHYS_DRAM_1 + (64 * 1024 * 1024))
> +#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START \
> +					+ (8 * 1024 * 1024))

Please see doc/README.memory-test and then eiter update the range to be
most of memory or drop these and add #undef CONFIG_CMD_MEMTEST.

> +#define CONFIG_SYS_HZ			1000 /* 1ms clock */
[snip]
> +#define CONFIG_SYS_HZ			1000

I see this is a copy/paste problem too from am335x_evm.h, can you fix
there and pcm051.h?

> +#define CONFIG_SERIAL_MULTI

Same (not needed anymore, not sure how it didn't get removed before).

[snip]
> +#define CONFIG_CMD_EEPROM
> +#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
> +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
> +#define CONFIG_SYS_I2C_MULTI_EEPROMS

Do you really have the EEPROM at 0x50 like the TI boards do (and then at
other offets for capes/daughter cards) ?

[snip]
> +#define	CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES * \
> +						CONFIG_SYS_NAND_ECCSTEPS)
> +
> +#define	CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE

Another problem duplicated from am335x_evm.h :(

[snip]
> +#define MTDPARTS_DEFAULT		"mtdparts=nand:" \
> +					"128k(spl)," \
> +					"1792k(boot)," \

This isn't quite right.  Your first 128k chunks are ROM-checked
redundant locations for SPL to live (hence the write of U-Boot at 512k
in).

> +#undef CONFIG_ENV_IS_NOWHERE

Did you ever set this?  I don't think so... on am335x_evm.h we do since
we can build for SPI env or NAND env.

All that said, yay for another board to try and help flush out generic
problems in am33xx land!

-- 
Tom
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