[U-Boot] [PATCH v4] imx: Add titanium board support (i.MX6 based)
Stefano Babic
sbabic at denx.de
Wed Apr 17 10:22:44 CEST 2013
On 16/04/2013 14:55, Stefan Roese wrote:
> Titanium is a i.MX6 based board from ProjectionDesign / Barco. This
> patch adds support for this board with the newly introduced NAND
> support for i.MX6.
>
> Signed-off-by: Stefan Roese <sr at denx.de>
> Cc: Stefano Babic <sbabic at denx.de>
> Cc: Fabio Estevam <fabio.estevam at freescale.com>
> ---
Hi Stefan,
> v4:
> - Use register defines instead of hardcoded addresses by including
> the headers in imximage.cfg
imximage.cfg is identical to V3. Maybe went something wrong by git
send-email ? ;-)
Best regards,
Stefano
> - Remove overwrite_console() as its not needed
> - Change CONFIG_BOOTCOMMAND
>
> v3:
> - Rebased on current master (ARM PR included, 2013.04-rc3)
> - Removed get_board_revision()
> - Fixed problem with MMC pad muxing in v2
>
> v2:
> - Fixed comment in imximage.imx
> - Use only english comments
> - Move include files to top of config header
> - Remove unnecessary loop in board_mmc_init()
> - Minor fixups
> - No magic values used any more
> - Increade NAND clock (GPMI IO) to 100MHz
> - CONFIG_ARP_TIMEOUT removed as its not needed
>
> MAINTAINERS | 2 +
> arch/arm/include/asm/arch-mx6/crm_regs.h | 7 +-
> board/freescale/titanium/Makefile | 36 ++++
> board/freescale/titanium/imximage.cfg | 173 +++++++++++++++
> board/freescale/titanium/titanium.c | 355 +++++++++++++++++++++++++++++++
> boards.cfg | 1 +
> include/configs/titanium.h | 278 ++++++++++++++++++++++++
> 7 files changed, 850 insertions(+), 2 deletions(-)
> create mode 100644 board/freescale/titanium/Makefile
> create mode 100644 board/freescale/titanium/imximage.cfg
> create mode 100644 board/freescale/titanium/titanium.c
> create mode 100644 include/configs/titanium.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index bbab5fe..fd595f4 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -877,6 +877,8 @@ Stefan Roese <sr at denx.de>
>
> x600 ARM926EJS (spear600 Soc)
>
> + titanium i.MX6Q
> +
> pdnb3 xscale/ixp
> scpu xscale/ixp
>
> diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
> index 7676457..cf5c694 100644
> --- a/arch/arm/include/asm/arch-mx6/crm_regs.h
> +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
> @@ -262,10 +262,13 @@ struct mxc_ccm_reg {
> /* Define the bits in register CS2CDR */
> #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21)
> #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
> +#define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21)
> #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18)
> #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
> +#define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18)
> #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16)
> #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16
> +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x3) << 16)
> #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12)
> #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
> #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9)
> @@ -415,8 +418,8 @@ struct mxc_ccm_reg {
> #define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3<<MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
> #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2
> #define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3<<MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
> -#define MXC_CCM_CCGR0_APBHDMA HCLK_OFFSET 4
> -#define MXC_CCM_CCGR0_AMASK (3<<MXC_CCM_CCGR0_APBHDMA)
> +#define MXC_CCM_CCGR0_APBHDMA_OFFSET 4
> +#define MXC_CCM_CCGR0_APBHDMA_MASK (3<<MXC_CCM_CCGR0_APBHDMA_OFFSET)
> #define MXC_CCM_CCGR0_ASRC_OFFSET 6
> #define MXC_CCM_CCGR0_ASRC_MASK (3<<MXC_CCM_CCGR0_ASRC_OFFSET)
> #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8
> diff --git a/board/freescale/titanium/Makefile b/board/freescale/titanium/Makefile
> new file mode 100644
> index 0000000..46827f8
> --- /dev/null
> +++ b/board/freescale/titanium/Makefile
> @@ -0,0 +1,36 @@
> +#
> +# Copyright (C) 2007, Guennadi Liakhovetski <lg at denx.de>
> +#
> +# (C) Copyright 2011 Freescale Semiconductor, Inc.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB = $(obj)lib$(BOARD).o
> +
> +COBJS := titanium.o
> +
> +SRCS := $(COBJS:.o=.c)
> +OBJS := $(addprefix $(obj),$(COBJS))
> +
> +$(LIB): $(obj).depend $(OBJS)
> + $(call cmd_link_o_target, $(OBJS))
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/board/freescale/titanium/imximage.cfg b/board/freescale/titanium/imximage.cfg
> new file mode 100644
> index 0000000..5661d58
> --- /dev/null
> +++ b/board/freescale/titanium/imximage.cfg
> @@ -0,0 +1,173 @@
> +/*
> + * Projectiondesign AS
> + * Derived from ./board/freescale/mx6qsabrelite/imximage.cfg
> + *
> + * Copyright (C) 2011 Freescale Semiconductor, Inc.
> + * Jason Liu <r64343 at freescale.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Refer docs/README.imxmage for more details about how-to configure
> + * and create imximage boot image
> + *
> + * The syntax is taken as close as possible with the kwbimage
> + */
> +
> +/* image version */
> +
> +IMAGE_VERSION 2
> +
> +/*
> + * Boot Device : one of
> + * sd, nand
> + */
> +BOOT_FROM nand
> +
> +/*
> + * Device Configuration Data (DCD)
> + *
> + * Each entry must have the format:
> + * Addr-type Address Value
> + *
> + * where:
> + * Addr-type register length (1,2 or 4 bytes)
> + * Address absolute address of the register
> + * value value to be stored in the register
> + */
> +DATA 4 0x020e05a8 0x00000030
> +DATA 4 0x020e05b0 0x00000030
> +DATA 4 0x020e0524 0x00000030
> +DATA 4 0x020e051c 0x00000030
> +
> +DATA 4 0x020e0518 0x00000030
> +DATA 4 0x020e050c 0x00000030
> +DATA 4 0x020e05b8 0x00000030
> +DATA 4 0x020e05c0 0x00000030
> +
> +DATA 4 0x020e05ac 0x00020030
> +DATA 4 0x020e05b4 0x00020030
> +DATA 4 0x020e0528 0x00020030
> +DATA 4 0x020e0520 0x00020030
> +
> +DATA 4 0x020e0514 0x00020030
> +DATA 4 0x020e0510 0x00020030
> +DATA 4 0x020e05bc 0x00020030
> +DATA 4 0x020e05c4 0x00020030
> +
> +DATA 4 0x020e056c 0x00020030
> +DATA 4 0x020e0578 0x00020030
> +DATA 4 0x020e0588 0x00020030
> +DATA 4 0x020e0594 0x00020030
> +
> +DATA 4 0x020e057c 0x00020030
> +DATA 4 0x020e0590 0x00003000
> +DATA 4 0x020e0598 0x00003000
> +DATA 4 0x020e058c 0x00000000
> +
> +DATA 4 0x020e059c 0x00003030
> +DATA 4 0x020e05a0 0x00003030
> +DATA 4 0x020e0784 0x00000030
> +DATA 4 0x020e0788 0x00000030
> +
> +DATA 4 0x020e0794 0x00000030
> +DATA 4 0x020e079c 0x00000030
> +DATA 4 0x020e07a0 0x00000030
> +DATA 4 0x020e07a4 0x00000030
> +
> +DATA 4 0x020e07a8 0x00000030
> +DATA 4 0x020e0748 0x00000030
> +DATA 4 0x020e074c 0x00000030
> +DATA 4 0x020e0750 0x00020000
> +
> +DATA 4 0x020e0758 0x00000000
> +DATA 4 0x020e0774 0x00020000
> +DATA 4 0x020e078c 0x00000030
> +DATA 4 0x020e0798 0x000C0000
> +
> +DATA 4 0x021b081c 0x33333333
> +DATA 4 0x021b0820 0x33333333
> +DATA 4 0x021b0824 0x33333333
> +DATA 4 0x021b0828 0x33333333
> +
> +DATA 4 0x021b481c 0x33333333
> +DATA 4 0x021b4820 0x33333333
> +DATA 4 0x021b4824 0x33333333
> +DATA 4 0x021b4828 0x33333333
> +
> +DATA 4 0x021b0018 0x00081740
> +
> +DATA 4 0x021b001c 0x00008000
> +DATA 4 0x021b000c 0x555A7975
> +DATA 4 0x021b0010 0xFF538E64
> +DATA 4 0x021b0014 0x01FF00DB
> +DATA 4 0x021b002c 0x000026D2
> +
> +DATA 4 0x021b0030 0x005B0E21
> +DATA 4 0x021b0008 0x09444040
> +DATA 4 0x021b0004 0x00025576
> +DATA 4 0x021b0040 0x00000017
> +DATA 4 0x021b0000 0x83190000 /* 32-bit data bus - sabrelite: 0x831A0000 */
> +
> +DATA 4 0x021b001c 0x04088032
> +DATA 4 0x021b001c 0x0408803A
> +DATA 4 0x021b001c 0x00008033
> +DATA 4 0x021b001c 0x0000803B
> +DATA 4 0x021b001c 0x00428031
> +DATA 4 0x021b001c 0x00428039
> +DATA 4 0x021b001c 0x09408030
> +DATA 4 0x021b001c 0x09408038
> +
> +DATA 4 0x021b001c 0x04008040
> +DATA 4 0x021b001c 0x04008048
> +DATA 4 0x021b0800 0xA1380003
> +DATA 4 0x021b4800 0xA1380003
> +DATA 4 0x021b0020 0x00005800
> +DATA 4 0x021b0818 0x00022227
> +DATA 4 0x021b4818 0x00022227
> +
> +DATA 4 0x021b083c 0x434B0350
> +DATA 4 0x021b0840 0x034C0359
> +DATA 4 0x021b483c 0x434B0350
> +DATA 4 0x021b4840 0x03650348
> +DATA 4 0x021b0848 0x4436383B
> +DATA 4 0x021b4848 0x39393341
> +DATA 4 0x021b0850 0x35373933
> +DATA 4 0x021b4850 0x48254A36
> +
> +DATA 4 0x021b080c 0x001F001F
> +DATA 4 0x021b0810 0x001F001F
> +
> +DATA 4 0x021b480c 0x00440044
> +DATA 4 0x021b4810 0x00440044
> +
> +DATA 4 0x021b08b8 0x00000800
> +DATA 4 0x021b48b8 0x00000800
> +
> +DATA 4 0x021b001c 0x00000000
> +DATA 4 0x021b0404 0x00011006
> +
> +/* set the default clock gate to save power */
> +DATA 4 0x020c4068 0x00C03F3F
> +DATA 4 0x020c406c 0x0030FC03
> +DATA 4 0x020c4070 0x0FFFC000
> +DATA 4 0x020c4074 0x3FF00000
> +DATA 4 0x020c4078 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */
> +DATA 4 0x020c407c 0x0F0000C3
> +DATA 4 0x020c4080 0x000003FF
> +
> +/* enable AXI cache for VDOA/VPU/IPU */
> +DATA 4 0x020e0010 0xF00000CF
> +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
> +DATA 4 0x020e0018 0x007F007F
> +DATA 4 0x020e001c 0x007F007F
> diff --git a/board/freescale/titanium/titanium.c b/board/freescale/titanium/titanium.c
> new file mode 100644
> index 0000000..7c200ce
> --- /dev/null
> +++ b/board/freescale/titanium/titanium.c
> @@ -0,0 +1,355 @@
> +/*
> + * Copyright (C) 2013 Stefan Roese <sr at denx.de>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/arch/iomux.h>
> +#include <asm/arch/mx6q_pins.h>
> +#include <asm/arch/crm_regs.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/gpio.h>
> +#include <asm/imx-common/iomux-v3.h>
> +#include <asm/imx-common/mxc_i2c.h>
> +#include <asm/imx-common/boot_mode.h>
> +#include <mmc.h>
> +#include <fsl_esdhc.h>
> +#include <micrel.h>
> +#include <miiphy.h>
> +#include <netdev.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
> + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
> + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
> +
> +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
> + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
> + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
> +
> +#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
> + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
> + PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
> +
> +#define SPI_PAD_CTRL (PAD_CTL_HYS | \
> + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
> + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
> +
> +#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
> + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
> + PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
> +
> +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
> + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
> + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
> + PAD_CTL_ODE | PAD_CTL_SRE_FAST)
> +
> +int dram_init(void)
> +{
> + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
> +
> + return 0;
> +}
> +
> +iomux_v3_cfg_t const uart1_pads[] = {
> + MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
> + MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +iomux_v3_cfg_t const uart2_pads[] = {
> + MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
> + MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +iomux_v3_cfg_t const uart4_pads[] = {
> + MX6_PAD_CSI0_DAT12__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
> + MX6_PAD_CSI0_DAT13__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
> +
> +struct i2c_pads_info i2c_pad_info0 = {
> + .scl = {
> + .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
> + .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO_5_27 | PC,
> + .gp = IMX_GPIO_NR(5, 27)
> + },
> + .sda = {
> + .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
> + .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO_5_26 | PC,
> + .gp = IMX_GPIO_NR(5, 26)
> + }
> +};
> +
> +struct i2c_pads_info i2c_pad_info2 = {
> + .scl = {
> + .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
> + .gpio_mode = MX6_PAD_GPIO_3__GPIO_1_3 | PC,
> + .gp = IMX_GPIO_NR(1, 3)
> + },
> + .sda = {
> + .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
> + .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC,
> + .gp = IMX_GPIO_NR(7, 11)
> + }
> +};
> +
> +iomux_v3_cfg_t const usdhc3_pads[] = {
> + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX6_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
> +};
> +
> +iomux_v3_cfg_t const enet_pads1[] = {
> + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + /* pin 35 - 1 (PHY_AD2) on reset */
> + MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + /* pin 32 - 1 - (MODE0) all */
> + MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + /* pin 31 - 1 - (MODE1) all */
> + MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + /* pin 28 - 1 - (MODE2) all */
> + MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + /* pin 27 - 1 - (MODE3) all */
> + MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
> + MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + /* pin 42 PHY nRST */
> + MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +iomux_v3_cfg_t const enet_pads2[] = {
> + MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +};
> +
> +iomux_v3_cfg_t nfc_pads[] = {
> + MX6_PAD_NANDF_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_NANDF_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_NANDF_WP_B__RAWNAND_RESETN | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_NANDF_RB0__RAWNAND_READY0 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_NANDF_CS0__RAWNAND_CE0N | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_NANDF_CS1__RAWNAND_CE1N | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_NANDF_CS2__RAWNAND_CE2N | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_NANDF_CS3__RAWNAND_CE3N | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_SD4_CMD__RAWNAND_RDN | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_SD4_CLK__RAWNAND_WRN | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_NANDF_D0__RAWNAND_D0 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_NANDF_D1__RAWNAND_D1 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_NANDF_D2__RAWNAND_D2 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_NANDF_D3__RAWNAND_D3 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_NANDF_D4__RAWNAND_D4 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_NANDF_D5__RAWNAND_D5 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_NANDF_D6__RAWNAND_D6 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_NANDF_D7__RAWNAND_D7 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + MX6_PAD_SD4_DAT0__RAWNAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +static void setup_gpmi_nand(void)
> +{
> + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> +
> + /* config gpmi nand iomux */
> + imx_iomux_v3_setup_multiple_pads(nfc_pads,
> + ARRAY_SIZE(nfc_pads));
> +
> + /* config gpmi and bch clock to 100 MHz */
> + clrsetbits_le32(&mxc_ccm->cs2cdr,
> + MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
> + MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
> + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
> + MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
> + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
> + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
> +
> + /* enable gpmi and bch clock gating */
> + setbits_le32(&mxc_ccm->CCGR4,
> + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
> + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
> + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
> + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
> + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
> +
> + /* enable apbh clock gating */
> + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
> +}
> +
> +static void setup_iomux_enet(void)
> +{
> + gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
> + gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
> + gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
> + gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
> + gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
> + gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
> + imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
> + gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
> +
> + /* Need delay 10ms according to KSZ9021 spec */
> + udelay(1000 * 10);
> + gpio_set_value(IMX_GPIO_NR(3, 23), 1);
> +
> + imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
> +}
> +
> +static void setup_iomux_uart(void)
> +{
> + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
> + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
> + imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
> +}
> +
> +#ifdef CONFIG_USB_EHCI_MX6
> +int board_ehci_hcd_init(int port)
> +{
> + return 0;
> +}
> +
> +#endif
> +
> +#ifdef CONFIG_FSL_ESDHC
> +struct fsl_esdhc_cfg usdhc_cfg[1] = {
> + { USDHC3_BASE_ADDR },
> +};
> +
> +int board_mmc_getcd(struct mmc *mmc)
> +{
> + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
> +
> + if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
> + gpio_direction_input(IMX_GPIO_NR(7, 0));
> + return !gpio_get_value(IMX_GPIO_NR(7, 0));
> + }
> +
> + return 0;
> +}
> +
> +int board_mmc_init(bd_t *bis)
> +{
> + /*
> + * Only one USDHC controller on titianium
> + */
> + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
> + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
> +
> + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
> +}
> +#endif
> +
> +int board_phy_config(struct phy_device *phydev)
> +{
> + /* min rx data delay */
> + ksz9021_phy_extended_write(phydev,
> + MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
> + /* min tx data delay */
> + ksz9021_phy_extended_write(phydev,
> + MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
> + /* max rx/tx clock delay, min rx/tx control */
> + ksz9021_phy_extended_write(phydev,
> + MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
> + if (phydev->drv->config)
> + phydev->drv->config(phydev);
> +
> + return 0;
> +}
> +
> +int board_eth_init(bd_t *bis)
> +{
> + int ret;
> +
> + setup_iomux_enet();
> +
> + ret = cpu_eth_init(bis);
> + if (ret)
> + printf("FEC MXC: %s:failed\n", __func__);
> +
> + return 0;
> +}
> +
> +int board_early_init_f(void)
> +{
> + setup_iomux_uart();
> +
> + return 0;
> +}
> +
> +/*
> + * Do not overwrite the console
> + * Use always serial for U-Boot console
> + */
> +int overwrite_console(void)
> +{
> + return 1;
> +}
> +
> +int board_init(void)
> +{
> + /* address of boot parameters */
> + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
> +
> + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
> + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
> +
> + setup_gpmi_nand();
> +
> + return 0;
> +}
> +
> +int checkboard(void)
> +{
> + puts("Board: Titanium\n");
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_CMD_BMODE
> +static const struct boot_mode board_boot_modes[] = {
> + /* NAND */
> + { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
> + /* 4 bit bus width */
> + { "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) },
> + { "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) },
> + { NULL, 0 },
> +};
> +#endif
> +
> +int misc_init_r(void)
> +{
> +#ifdef CONFIG_CMD_BMODE
> + add_board_boot_modes(board_boot_modes);
> +#endif
> +
> + return 0;
> +}
> diff --git a/boards.cfg b/boards.cfg
> index f785da8..b162b83 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -259,6 +259,7 @@ mx6qarm2 arm armv7 mx6qarm2 freesca
> mx6qsabreauto arm armv7 mx6qsabreauto freescale mx6 mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg
> mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
> mx6qsabresd arm armv7 mx6qsabresd freescale mx6 mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
> +titanium arm armv7 titanium freescale mx6 titanium:IMX_CONFIG=board/freescale/titanium/imximage.cfg
> eco5pk arm armv7 eco5pk 8dtech omap3
> nitrogen6dl arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024
> nitrogen6dl2g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048
> diff --git a/include/configs/titanium.h b/include/configs/titanium.h
> new file mode 100644
> index 0000000..9ecd259
> --- /dev/null
> +++ b/include/configs/titanium.h
> @@ -0,0 +1,278 @@
> +/*
> + * Copyright (C) 2013 Stefan Roese <sr at denx.de>
> + *
> + * Configuration settings for the ProjectionDesign / Barco
> + * Titanium board.
> + *
> + * Based on mx6qsabrelite.h which is:
> + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#include <asm/arch/imx-regs.h>
> +#include <asm/imx-common/gpio.h>
> +
> +#define CONFIG_MX6
> +#define CONFIG_MX6Q
> +#define CONFIG_DISPLAY_CPUINFO
> +#define CONFIG_DISPLAY_BOARDINFO
> +
> +#define MACH_TYPE_TITANIUM 3769
> +#define CONFIG_MACH_TYPE MACH_TYPE_TITANIUM
> +
> +#define CONFIG_CMDLINE_TAG
> +#define CONFIG_SETUP_MEMORY_TAGS
> +#define CONFIG_INITRD_TAG
> +#define CONFIG_REVISION_TAG
> +
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
> +
> +#define CONFIG_BOARD_EARLY_INIT_F
> +#define CONFIG_MISC_INIT_R
> +#define CONFIG_MXC_GPIO
> +
> +#define CONFIG_MXC_UART
> +#define CONFIG_MXC_UART_BASE UART1_BASE
> +
> +/* I2C Configs */
> +#define CONFIG_CMD_I2C
> +#define CONFIG_I2C_MULTI_BUS
> +#define CONFIG_I2C_MXC
> +#define CONFIG_SYS_I2C_SPEED 100000
> +
> +/* MMC Configs */
> +#define CONFIG_FSL_ESDHC
> +#define CONFIG_FSL_USDHC
> +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
> +#define CONFIG_SYS_FSL_USDHC_NUM 1
> +
> +#define CONFIG_MMC
> +#define CONFIG_CMD_MMC
> +#define CONFIG_GENERIC_MMC
> +#define CONFIG_BOUNCE_BUFFER
> +#define CONFIG_CMD_EXT2
> +#define CONFIG_CMD_FAT
> +#define CONFIG_DOS_PARTITION
> +
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_MII
> +#define CONFIG_CMD_NET
> +#define CONFIG_FEC_MXC
> +#define CONFIG_MII
> +#define IMX_FEC_BASE ENET_BASE_ADDR
> +#define CONFIG_FEC_XCV_TYPE RGMII
> +#define CONFIG_ETHPRIME "FEC"
> +#define CONFIG_FEC_MXC_PHYADDR 4
> +#define CONFIG_PHYLIB
> +#define CONFIG_PHY_MICREL
> +#define CONFIG_PHY_MICREL_KSZ9021
> +
> +/* USB Configs */
> +#define CONFIG_CMD_USB
> +#define CONFIG_CMD_FAT
> +#define CONFIG_USB_EHCI
> +#define CONFIG_USB_EHCI_MX6
> +#define CONFIG_USB_STORAGE
> +#define CONFIG_MXC_USB_PORT 1
> +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
> +#define CONFIG_MXC_USB_FLAGS 0
> +
> +/* Miscellaneous commands */
> +#define CONFIG_CMD_BMODE
> +
> +/* allow to overwrite serial and ethaddr */
> +#define CONFIG_ENV_OVERWRITE
> +#define CONFIG_CONS_INDEX 1
> +#define CONFIG_BAUDRATE 115200
> +
> +/* Command definition */
> +#include <config_cmd_default.h>
> +
> +#undef CONFIG_CMD_IMLS
> +
> +#define CONFIG_BOOTDELAY 3
> +
> +#define CONFIG_LOADADDR 0x12000000
> +#define CONFIG_SYS_TEXT_BASE 0x17800000
> +
> +#define CONFIG_SYS_MEMTEST_START 0x10000000
> +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (500 << 20))
> +
> +#define CONFIG_HOSTNAME titanium
> +#define CONFIG_UBI_PART ubi
> +#define CONFIG_UBIFS_VOLUME rootfs0
> +
> +#define MTDIDS_DEFAULT "nand0=gpmi-nand"
> +#define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:16M(uboot),512k(env1)," \
> + "512k(env2),-(ubi)"
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "kernel=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
> + "kernel_fs=/boot/uImage\0" \
> + "kernel_addr=11000000\0" \
> + "dtb=" __stringify(CONFIG_HOSTNAME) "/" \
> + __stringify(CONFIG_HOSTNAME) ".dtb\0" \
> + "dtb_fs=/boot/" __stringify(CONFIG_HOSTNAME) ".dtb\0" \
> + "dtb_addr=12800000\0" \
> + "script=boot.scr\0" \
> + "uimage=uImage\0" \
> + "console=ttymxc0\0" \
> + "baudrate=115200\0" \
> + "fdt_high=0xffffffff\0" \
> + "initrd_high=0xffffffff\0" \
> + "mmcdev=0\0" \
> + "mmcpart=1\0" \
> + "uimage=uImage\0" \
> + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}" \
> + " ${script}\0" \
> + "bootscript=echo Running bootscript from mmc ...; source\0" \
> + "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
> + "mmcroot=/dev/mmcblk0p2\0" \
> + "mmcargs=setenv bootargs console=${console},${baudrate} " \
> + "root=${mmcroot} rootwait rw\0" \
> + "bootmmc=run mmcargs; fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}" \
> + " ${uimage}; bootm\0" \
> + "addip=setenv bootargs ${bootargs} " \
> + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
> + ":${hostname}:${netdev}:off panic=1\0" \
> + "addcon=setenv bootargs ${bootargs} console=ttymxc0," \
> + "${baudrate}\0" \
> + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
> + "rootpath=/opt/eldk-5.3/armv7a/rootfs-minimal-mtdutils\0" \
> + "nfsargs=setenv bootargs root=/dev/nfs rw " \
> + "nfsroot=${serverip}:${rootpath}\0" \
> + "ubifs=" __stringify(CONFIG_HOSTNAME) "/ubifs.img\0" \
> + "part=" __stringify(CONFIG_UBI_PART) "\0" \
> + "boot_vol=0\0" \
> + "vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \
> + "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \
> + "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \
> + " ${filesize}\0" \
> + "upd_ubifs=run load_ubifs update_ubifs\0" \
> + "init_ubi=nand erase.part ubi;ubi part ${part};" \
> + "ubi create ${vol} c800000\0" \
> + "mtdids=" MTDIDS_DEFAULT "\0" \
> + "mtdparts=" MTDPARTS_DEFAULT "\0" \
> + "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \
> + " addcon addmtd;" \
> + "bootm ${kernel_addr} - ${dtb_addr}\0" \
> + "ubifsargs=set bootargs ubi.mtd=ubi " \
> + "root=ubi:rootfs${boot_vol} rootfstype=ubifs\0" \
> + "ubifs_mount=ubi part ubi;ubifsmount ubi:rootfs${boot_vol}\0" \
> + "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \
> + "ubifsload ${dtb_addr} ${dtb_fs};\0" \
> + "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \
> + "addmtd;bootm ${kernel_addr} - ${dtb_addr}\0" \
> + "load_kernel=tftp ${kernel_addr} ${kernel}\0" \
> + "load_dtb=tftp ${dtb_addr} ${dtb}\0" \
> + "net_nfs=run load_dtb load_kernel; " \
> + "run nfsargs addip addcon addmtd;" \
> + "bootm ${kernel_addr} - ${dtb_addr}\0" \
> + "delenv=env default -a -f; saveenv; reset\0"
> +
> +#define CONFIG_BOOTCOMMAND "run bootnfs"
> +
> +/* Miscellaneous configurable options */
> +#define CONFIG_SYS_LONGHELP
> +#define CONFIG_SYS_HUSH_PARSER
> +#define CONFIG_SYS_PROMPT "Titanium > "
> +#define CONFIG_AUTO_COMPLETE
> +#define CONFIG_CMDLINE_EDITING
> +#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
> +
> +#define CONFIG_SYS_CBSIZE 256
> +
> +/* Print Buffer Size */
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
> + sizeof(CONFIG_SYS_PROMPT) + 16)
> +#define CONFIG_SYS_MAXARGS 16
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> +
> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> +#define CONFIG_SYS_HZ 1000
> +
> +/* Physical Memory Map */
> +#define CONFIG_NR_DRAM_BANKS 1
> +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
> +#define PHYS_SDRAM_SIZE (512 << 20)
> +
> +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
> +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
> +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
> +
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_ADDR \
> + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +/* FLASH and environment organization */
> +#define CONFIG_SYS_NO_FLASH
> +
> +/* Enable NAND support */
> +#define CONFIG_CMD_NAND
> +#define CONFIG_CMD_NAND_TRIMFFS
> +#define CONFIG_CMD_TIME
> +
> +#ifdef CONFIG_CMD_NAND
> +
> +/* NAND stuff */
> +#define CONFIG_NAND_MXS
> +#define CONFIG_SYS_MAX_NAND_DEVICE 1
> +#define CONFIG_SYS_NAND_BASE 0x40000000
> +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
> +#define CONFIG_SYS_NAND_ONFI_DETECTION
> +
> +/* DMA stuff, needed for GPMI/MXS NAND support */
> +#define CONFIG_APBH_DMA
> +#define CONFIG_APBH_DMA_BURST
> +#define CONFIG_APBH_DMA_BURST8
> +
> +/* Environment in NAND */
> +#define CONFIG_ENV_IS_IN_NAND
> +#define CONFIG_ENV_OFFSET (16 << 20)
> +#define CONFIG_ENV_SECT_SIZE (128 << 10)
> +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
> +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + (512 << 10))
> +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
> +
> +#else /* CONFIG_CMD_NAND */
> +
> +/* Environment in MMC */
> +#define CONFIG_ENV_SIZE (8 << 10)
> +#define CONFIG_ENV_IS_IN_MMC
> +#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
> +#define CONFIG_SYS_MMC_ENV_DEV 0
> +
> +#endif /* CONFIG_CMD_NAND */
> +
> +/* UBI/UBIFS config options */
> +#define CONFIG_LZO
> +#define CONFIG_MTD_DEVICE
> +#define CONFIG_MTD_PARTITIONS
> +#define CONFIG_RBTREE
> +#define CONFIG_CMD_MTDPARTS
> +#define CONFIG_CMD_UBI
> +#define CONFIG_CMD_UBIFS
> +
> +#define CONFIG_OF_LIBFDT
> +#define CONFIG_CMD_BOOTZ
> +
> +#ifndef CONFIG_SYS_DCACHE_OFF
> +#define CONFIG_CMD_CACHE
> +#endif
> +
> +#endif /* __CONFIG_H */
>
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
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