[U-Boot] [PATCH V2 6/6] arm: mx5: Add support for DENX M53EVK
Benoît Thébaudeau
benoit.thebaudeau at advansee.com
Sun Apr 21 19:16:24 CEST 2013
Dear Marek Vasut,
On Sunday, April 21, 2013 5:52:27 PM, Marek Vasut wrote:
> Add basic support for the DENX M53EVK board. Currently supported is:
> MMC (incl. booting)
^
Can you clarify this, please? spl_boot_device() points only to NAND, so you're
clearly talking about hardware MMC boot, and not about hardware NAND boot
followed by SPL payload fetched from MMC. But MMC boot does not need SPL here,
in which case you will have to generate a simple u-boot.imx, or you will rather
want to use u-boot-with-spl.imx for SD (NAND header dropped to leave room for
MBR). And in the latter case, why have spl_boot_device() point to NAND for MMC
boot?
> NAND (incl. booting)
> Ethernet, I2C, USB, SATA, RTC.
>
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Albert ARIBAUD <albert.u.boot at aribaud.net>
> Cc: Benoît Thébaudeau <benoit.thebaudeau at advansee.com>
> Cc: Fabio Estevam <fabio.estevam at freescale.com>
> Cc: Scott Wood <scottwood at freescale.com>
> Cc: Stefano Babic <sbabic at denx.de>
> Cc: Tom Rini <trini at ti.com>
> Cc: Wolfgang Denk <wd at denx.de>
> ---
> MAINTAINERS | 1 +
> board/denx/m53evk/Makefile | 40 ++++
> board/denx/m53evk/imximage.cfg | 108 +++++++++++
> board/denx/m53evk/m53evk.c | 420
> ++++++++++++++++++++++++++++++++++++++++
> boards.cfg | 1 +
> include/configs/m53evk.h | 255 ++++++++++++++++++++++++
> 6 files changed, 825 insertions(+)
> create mode 100644 board/denx/m53evk/Makefile
> create mode 100644 board/denx/m53evk/imximage.cfg
> create mode 100644 board/denx/m53evk/m53evk.c
> create mode 100644 include/configs/m53evk.h
>
> V2: Init M4IF and WEIM
> Clean up config file
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 643a5ac..e109be6 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -954,6 +954,7 @@ Marek Vasut <marek.vasut at gmail.com>
> mx23_olinuxino i.MX23
> m28evk i.MX28
> sc_sps_1 i.MX28
> + m53evk i.MX53
>
> Hugo Villeneuve <hugo.villeneuve at lyrtech.com>
>
> diff --git a/board/denx/m53evk/Makefile b/board/denx/m53evk/Makefile
> new file mode 100644
> index 0000000..bfb040a
> --- /dev/null
> +++ b/board/denx/m53evk/Makefile
> @@ -0,0 +1,40 @@
> +#
> +# DENX M53EVK
> +# Copyright (C) 2012-2013 Marek Vasut <marex at denx.de>
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB = $(obj)lib$(BOARD).o
> +
> +COBJS := m53evk.o
> +
> +SRCS := $(COBJS:.o=.c)
> +OBJS := $(addprefix $(obj),$(COBJS))
> +
> +$(LIB): $(obj).depend $(OBJS)
> + $(call cmd_link_o_target, $(OBJS))
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/board/denx/m53evk/imximage.cfg b/board/denx/m53evk/imximage.cfg
> new file mode 100644
> index 0000000..3d60de0
> --- /dev/null
> +++ b/board/denx/m53evk/imximage.cfg
> @@ -0,0 +1,108 @@
> +/*
> + * DENX M53 DRAM init values
> + * Copyright (C) 2012-2013 Marek Vasut <marex at denx.de>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not write to the Free Software
> + * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
> + * MA 02110-1301 USA
> + *
> + * Refer docs/README.imxmage for more details about how-to configure
> + * and create imximage boot image
> + *
> + * The syntax is taken as close as possible with the kwbimage
> + */
> +/* image version */
> +IMAGE_VERSION 2
> +
> +/*
> + * Boot Device : one of
> + * spi, sd, nand
> + */
> +BOOT_FROM nand
> +
> +/*
> + * Device Configuration Data (DCD)
> + *
> + * Each entry must have the format:
> + * Addr-type Address Value
> + *
> + * where:
> + * Addr-type register length (1,2 or 4 bytes)
> + * Address absolute address of the register
> + * value value to be stored in the register
> + */
> +DATA 4 0x53fa86f4 0x00000000 /* GRP_DDRMODE_CTL */
> +DATA 4 0x53fa8714 0x00000000 /* GRP_DDRMODE */
> +DATA 4 0x53fa86fc 0x00000000 /* GRP_DDRPKE */
> +DATA 4 0x53fa8724 0x04000000 /* GRP_DDR_TYPE */
> +
> +DATA 4 0x53fa872c 0x00300000 /* GRP_B3DS */
> +DATA 4 0x53fa8554 0x00300000 /* DRAM_DQM3 */
> +DATA 4 0x53fa8558 0x00300040 /* DRAM_SDQS3 */
> +
> +DATA 4 0x53fa8728 0x00300000 /* GRP_B2DS */
> +DATA 4 0x53fa8560 0x00300000 /* DRAM_DQM2 */
> +DATA 4 0x53fa8568 0x00300040 /* DRAM_SDQS2 */
> +
> +DATA 4 0x53fa871c 0x00300000 /* GRP_B1DS */
> +DATA 4 0x53fa8594 0x00300000 /* DRAM_DQM1 */
> +DATA 4 0x53fa8590 0x00300040 /* DRAM_SDQS1 */
> +
> +DATA 4 0x53fa8718 0x00300000 /* GRP_B0DS */
> +DATA 4 0x53fa8584 0x00300000 /* DRAM_DQM0 */
> +DATA 4 0x53fa857c 0x00300040 /* DRAM_SDQS0 */
> +
> +DATA 4 0x53fa8578 0x00300000 /* DRAM_SDCLK_0 */
> +DATA 4 0x53fa8570 0x00300000 /* DRAM_SDCLK_1 */
> +
> +DATA 4 0x53fa8574 0x00300000 /* DRAM_CAS */
> +DATA 4 0x53fa8588 0x00300000 /* DRAM_RAS */
> +DATA 4 0x53fa86f0 0x00300000 /* GRP_ADDDS */
> +DATA 4 0x53fa8720 0x00300000 /* GRP_CTLDS */
> +
> +DATA 4 0x53fa8564 0x00300040 /* DRAM_SDODT1 */
> +DATA 4 0x53fa8580 0x00300040 /* DRAM_SDODT0 */
> +
> +/* ESDCTL */
> +DATA 4 0x63fd9088 0x32383535
> +DATA 4 0x63fd9090 0x40383538
> +DATA 4 0x63fd907c 0x0136014d
> +DATA 4 0x63fd9080 0x01510141
> +
> +DATA 4 0x63fd9018 0x00011740
> +DATA 4 0x63fd9000 0xc3190000
> +DATA 4 0x63fd900c 0x555952e3
> +DATA 4 0x63fd9010 0xb68e8b63
> +DATA 4 0x63fd9014 0x01ff00db
> +DATA 4 0x63fd902c 0x000026d2
> +DATA 4 0x63fd9030 0x009f0e21
> +DATA 4 0x63fd9008 0x12273030
> +DATA 4 0x63fd9004 0x0002002d
> +DATA 4 0x63fd901c 0x00008032
> +DATA 4 0x63fd901c 0x00008033
> +DATA 4 0x63fd901c 0x00028031
> +DATA 4 0x63fd901c 0x092080b0
> +DATA 4 0x63fd901c 0x04008040
> +DATA 4 0x63fd901c 0x0000803a
> +DATA 4 0x63fd901c 0x0000803b
> +DATA 4 0x63fd901c 0x00028039
> +DATA 4 0x63fd901c 0x09208138
> +DATA 4 0x63fd901c 0x04008048
> +DATA 4 0x63fd9020 0x00001800
> +DATA 4 0x63fd9040 0x04b80003
> +DATA 4 0x63fd9058 0x00022227
> +DATA 4 0x63fd901c 0x00000000
> diff --git a/board/denx/m53evk/m53evk.c b/board/denx/m53evk/m53evk.c
> new file mode 100644
> index 0000000..07fd6f4
> --- /dev/null
> +++ b/board/denx/m53evk/m53evk.c
> @@ -0,0 +1,420 @@
> +/*
> + * DENX M53 module
> + *
> + * Copyright (C) 2012-2013 Marek Vasut <marex at denx.de>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/arch/mx5x_pins.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/arch/crm_regs.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/iomux.h>
> +#include <asm/arch/spl.h>
> +#include <asm/errno.h>
> +#include <netdev.h>
> +#include <i2c.h>
> +#include <mmc.h>
> +#include <spl.h>
> +#include <fsl_esdhc.h>
> +#include <asm/gpio.h>
> +#include <usb/ehci-fsl.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int dram_init(void)
> +{
> + u32 size1, size2;
> +
> + size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
> + size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
> +
> + gd->ram_size = size1 + size2;
> +
> + return 0;
> +}
> +void dram_init_banksize(void)
> +{
> + gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
> + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
> +
> + gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
> + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
> +}
> +
> +u32 get_board_rev(void)
> +{
> + struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
> + struct fuse_bank *bank = &iim->bank[0];
> + struct fuse_bank0_regs *fuse =
> + (struct fuse_bank0_regs *)bank->fuse_regs;
> + int rev = readl(&fuse->gp[6]);
> +
> + return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
> +}
> +
> +static void setup_iomux_uart(void)
> +{
> + mxc_request_iomux(MX53_PIN_ATA_BUFFER_EN, IOMUX_CONFIG_ALT3);
> + mxc_request_iomux(MX53_PIN_ATA_DMARQ, IOMUX_CONFIG_ALT3);
> +
> + mxc_iomux_set_pad(MX53_PIN_ATA_BUFFER_EN,
> + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
> + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
> + PAD_CTL_HYS_ENABLE);
> + mxc_iomux_set_pad(MX53_PIN_ATA_DMARQ,
> + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
> + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
> + PAD_CTL_HYS_ENABLE);
> +
> + mxc_iomux_set_input(MX53_UART2_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3);
> +}
> +
> +#ifdef CONFIG_USB_EHCI_MX5
> +int board_ehci_hcd_init(int port)
> +{
> + if (port == 0) {
> + /* USB OTG PWRON */
> + mxc_request_iomux(MX53_PIN_GPIO_4, IOMUX_CONFIG_ALT1);
> + mxc_iomux_set_pad(MX53_PIN_GPIO_4,
> + PAD_CTL_PKE_ENABLE |
> + PAD_CTL_100K_PD |
> + PAD_CTL_DRV_HIGH
> + );
> + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_4), 0);
> +
> + /* USB OTG Over Current */
> + mxc_request_iomux(MX53_PIN_GPIO_18, IOMUX_CONFIG_ALT1);
> + mxc_iomux_set_input(MX53_USBOH3_IPP_IND_OTG_OC_SELECT_INPUT, 1);
> + } else if (port == 1) {
> + /* USB Host PWRON */
> + mxc_request_iomux(MX53_PIN_GPIO_2, IOMUX_CONFIG_ALT1);
> + mxc_iomux_set_pad(MX53_PIN_GPIO_2,
> + PAD_CTL_PKE_ENABLE |
> + PAD_CTL_100K_PD |
> + PAD_CTL_DRV_HIGH
> + );
> + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_2), 0);
> +
> + /* USB Host Over Current */
> + mxc_request_iomux(MX53_PIN_GPIO_3, IOMUX_CONFIG_ALT6);
> + mxc_iomux_set_input(MX53_USBOH3_IPP_IND_UH1_OC_SELECT_INPUT, 1);
> + }
> +
> + return 0;
> +}
> +#endif
> +
> +static void setup_iomux_fec(void)
> +{
> + /* MDIO IOMUX */
> + mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
> +
> + /* FEC 0 IOMUX */
> + mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
> +
> + /* FEC 1 IOMUX */
> + mxc_request_iomux(MX53_PIN_KEY_COL0, IOMUX_CONFIG_ALT6); /* RXD3 */
> + mxc_request_iomux(MX53_PIN_KEY_ROW0, IOMUX_CONFIG_ALT6); /* TX_ER */
> + mxc_request_iomux(MX53_PIN_KEY_COL1, IOMUX_CONFIG_ALT6); /* RX_CLK */
> + mxc_request_iomux(MX53_PIN_KEY_ROW1, IOMUX_CONFIG_ALT6); /* COL */
> + mxc_request_iomux(MX53_PIN_KEY_COL2, IOMUX_CONFIG_ALT6); /* RXD2 */
> + mxc_request_iomux(MX53_PIN_KEY_ROW2, IOMUX_CONFIG_ALT6); /* TXD2 */
> + mxc_request_iomux(MX53_PIN_KEY_COL3, IOMUX_CONFIG_ALT6); /* CRS */
> + mxc_request_iomux(MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT6); /* TXD3 */
> +
> + /* MDIO PADs */
> + mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
> + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
> + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
> + PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
> + mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
> + mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
> +
> + /* FEC 0 PADs */
> + mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
> + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
> + mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
> + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
> + mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
> + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
> + mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
> + mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
> + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
> + mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
> + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
> + mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
> + mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
> +
> + /* FEC 1 PADs */
> + mxc_iomux_set_pad(MX53_PIN_KEY_COL0, /* RXD3 */
> + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
> + mxc_iomux_set_pad(MX53_PIN_KEY_ROW0, /* TX_ER */
> + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
> + mxc_iomux_set_pad(MX53_PIN_KEY_COL1, /* RX_CLK */
> + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
> + mxc_iomux_set_pad(MX53_PIN_KEY_ROW1, /* COL */
> + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
> + mxc_iomux_set_pad(MX53_PIN_KEY_COL2, /* RXD2 */
> + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
> + mxc_iomux_set_pad(MX53_PIN_KEY_ROW2, /* TXD2 */
> + PAD_CTL_DRV_HIGH);
> + mxc_iomux_set_pad(MX53_PIN_KEY_COL3, /* CRS */
> + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
> + mxc_iomux_set_pad(MX53_PIN_GPIO_19, /* TXD3 */
> + PAD_CTL_DRV_HIGH);
> +}
> +
> +#ifdef CONFIG_FSL_ESDHC
> +struct fsl_esdhc_cfg esdhc_cfg = {
> + MMC_SDHC1_BASE_ADDR,
> +};
> +
> +int board_mmc_getcd(struct mmc *mmc)
> +{
> + mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1);
> + gpio_direction_input(IMX_GPIO_NR(1, 1));
> +
> + return !gpio_get_value(IMX_GPIO_NR(1, 1));
> +}
> +
> +int board_mmc_init(bd_t *bis)
> +{
> + esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
> +
> + mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX53_PIN_SD1_DATA0,
> + IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX53_PIN_SD1_DATA1,
> + IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX53_PIN_SD1_DATA2,
> + IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX53_PIN_SD1_DATA3,
> + IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX53_PIN_EIM_DA13,
> + IOMUX_CONFIG_ALT1);
> +
> + mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
> + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
> + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
> + PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
> + mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
> + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
> + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
> + PAD_CTL_DRV_HIGH);
> + mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
> + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
> + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
> + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
> + mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
> + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
> + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
> + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
> + mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
> + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
> + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
> + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
> + mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
> + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
> + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
> + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
> +
> + /* GPIO 2_31 is SD power */
> + mxc_request_iomux(MX53_PIN_EIM_EB3, IOMUX_CONFIG_ALT1);
> + gpio_direction_output(IMX_GPIO_NR(2, 31), 0);
> +
> + return fsl_esdhc_initialize(bis, &esdhc_cfg);
> +}
> +#endif
> +
> +static void setup_iomux_i2c(void)
> +{
> + mxc_request_iomux(MX53_PIN_EIM_D16,
> + IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
> + mxc_request_iomux(MX53_PIN_EIM_EB2,
> + IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
> +
> + mxc_iomux_set_pad(MX53_PIN_EIM_D16,
> + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
> + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
> + PAD_CTL_PUE_PULL |
> + PAD_CTL_ODE_OPENDRAIN_ENABLE);
> + mxc_iomux_set_pad(MX53_PIN_EIM_EB2,
> + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
> + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
> + PAD_CTL_PUE_PULL |
> + PAD_CTL_ODE_OPENDRAIN_ENABLE);
> +
> + mxc_iomux_set_input(MX53_I2C2_IPP_SDA_IN_SELECT_INPUT, 0x1);
> + mxc_iomux_set_input(MX53_I2C2_IPP_SCL_IN_SELECT_INPUT, 0x1);
> +}
> +
> +static void setup_iomux_nand(void)
> +{
> + mxc_request_iomux(MX53_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX53_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX53_PIN_NANDF_CLE, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX53_PIN_NANDF_ALE, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX53_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX53_PIN_NANDF_RB0, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX53_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX53_PIN_ATA_DATA0, IOMUX_CONFIG_ALT3);
> + mxc_request_iomux(MX53_PIN_ATA_DATA1, IOMUX_CONFIG_ALT3);
> + mxc_request_iomux(MX53_PIN_ATA_DATA2, IOMUX_CONFIG_ALT3);
> + mxc_request_iomux(MX53_PIN_ATA_DATA3, IOMUX_CONFIG_ALT3);
> + mxc_request_iomux(MX53_PIN_ATA_DATA4, IOMUX_CONFIG_ALT3);
> + mxc_request_iomux(MX53_PIN_ATA_DATA5, IOMUX_CONFIG_ALT3);
> + mxc_request_iomux(MX53_PIN_ATA_DATA6, IOMUX_CONFIG_ALT3);
> + mxc_request_iomux(MX53_PIN_ATA_DATA7, IOMUX_CONFIG_ALT3);
> +
> + mxc_iomux_set_pad(MX53_PIN_NANDF_WE_B, PAD_CTL_DRV_HIGH);
> + mxc_iomux_set_pad(MX53_PIN_NANDF_RE_B, PAD_CTL_DRV_HIGH);
> + mxc_iomux_set_pad(MX53_PIN_NANDF_CLE, PAD_CTL_DRV_HIGH);
> + mxc_iomux_set_pad(MX53_PIN_NANDF_ALE, PAD_CTL_DRV_HIGH);
> + mxc_iomux_set_pad(MX53_PIN_NANDF_WP_B, PAD_CTL_PUE_PULL |
> + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE);
> + mxc_iomux_set_pad(MX53_PIN_NANDF_RB0, PAD_CTL_PUE_PULL |
> + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE);
> + mxc_iomux_set_pad(MX53_PIN_NANDF_CS0, PAD_CTL_DRV_HIGH);
> + mxc_iomux_set_pad(MX53_PIN_ATA_DATA0, PAD_CTL_DRV_HIGH |
> + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE);
> + mxc_iomux_set_pad(MX53_PIN_ATA_DATA1, PAD_CTL_DRV_HIGH |
> + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE);
> + mxc_iomux_set_pad(MX53_PIN_ATA_DATA2, PAD_CTL_DRV_HIGH |
> + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE);
> + mxc_iomux_set_pad(MX53_PIN_ATA_DATA3, PAD_CTL_DRV_HIGH |
> + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE);
> + mxc_iomux_set_pad(MX53_PIN_ATA_DATA4, PAD_CTL_DRV_HIGH |
> + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE);
> + mxc_iomux_set_pad(MX53_PIN_ATA_DATA5, PAD_CTL_DRV_HIGH |
> + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE);
> + mxc_iomux_set_pad(MX53_PIN_ATA_DATA6, PAD_CTL_DRV_HIGH |
> + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE);
> + mxc_iomux_set_pad(MX53_PIN_ATA_DATA7, PAD_CTL_DRV_HIGH |
> + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE);
> +}
> +
> +static void m53_set_clock(void)
> +{
> + int ret;
> + const uint32_t ref_clk = MXC_HCLK;
> + const uint32_t dramclk = 400;
> + uint32_t cpuclk;
> +
> + mxc_request_iomux(MX53_PIN_GPIO_10, IOMUX_CONFIG_GPIO);
> + mxc_iomux_set_pad(MX53_PIN_GPIO_10, PAD_CTL_DRV_HIGH |
> + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE);
> + gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_GPIO_10));
> +
> + /* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
> + cpuclk = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_10)) ? 1200 : 800;
> +
> + ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
> + if (ret)
> + printf("CPU: Switch CPU clock to %dMHz failed\n", cpuclk);
> +
> + ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
> + if (ret) {
> + printf("CPU: Switch peripheral clock to %dMHz failed\n",
> + dramclk);
> + }
> +
> + ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
> + if (ret)
> + printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk);
> +}
> +
> +static void m53_set_nand(void)
> +{
> + u32 i;
> +
> + #define M4IF_GENP_WEIM_MM 0x00000001
> + #define WEIM_GCR2_MUX16_BYP_GRANT 0x00001000
> +
> + /* NAND flash is muxed on ATA pins */
> + setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM);
This should be clrbits_le32().
> +
> + /* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
> + for (i = 0x4; i < 0x94; i += 0x18)
> + clrbits_le32(WEIM_BASE_ADDR + i, WEIM_GCR2_MUX16_BYP_GRANT);
> +
> + mxc_set_clock(0, 33, MXC_NFC_CLK);
> + enable_nfc_clk(1);
> +}
> +
> +int board_early_init_f(void)
> +{
> + setup_iomux_uart();
> + setup_iomux_fec();
> + setup_iomux_i2c();
> + setup_iomux_nand();
> +
> + m53_set_clock();
> +
> + mxc_set_sata_internal_clock();
> +
> + /* NAND clock @ 33MHz */
> + m53_set_nand();
> +
> + return 0;
> +}
> +
> +int board_init(void)
> +{
> + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
> +
> + return 0;
> +}
> +
> +int checkboard(void)
> +{
> + puts("Board: DENX M53EVK\n");
> +
> + return 0;
> +}
> +
> +/*
> + * NAND SPL
> + */
> +#ifdef CONFIG_SPL_BUILD
> +void spl_board_init(void)
> +{
> + setup_iomux_nand();
> + m53_set_clock();
> + m53_set_nand();
> +}
> +
> +u32 spl_boot_device(void)
> +{
> + return BOOT_DEVICE_NAND;
> +}
> +#endif
> diff --git a/boards.cfg b/boards.cfg
> index 31483d6..822ae01 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -246,6 +246,7 @@ am335x_evm_usbspl arm armv7
> am335x ti
> ti814x_evm arm armv7 ti814x ti
> am33xx
> pcm051 arm armv7 pcm051
> phytec am33xx pcm051
> highbank arm armv7 highbank -
> highbank
> +m53evk arm armv7 m53evk
> denx mx5 m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg
> mx51_efikamx arm armv7 mx51_efikamx
> genesi mx5
> mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg
> mx51_efikasb arm armv7 mx51_efikamx
> genesi mx5
> mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg
> mx51evk arm armv7 mx51evk
> freescale mx5
> mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg
> diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h
> new file mode 100644
> index 0000000..78e1226
> --- /dev/null
> +++ b/include/configs/m53evk.h
> @@ -0,0 +1,255 @@
> +/*
> + * DENX M53 configuration
> + * Copyright (C) 2012-2013 Marek Vasut <marex at denx.de>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __M53EVK_CONFIG_H__
> +#define __M53EVK_CONFIG_H__
> +
> +#define CONFIG_MX53
> +#define CONFIG_MXC_GPIO
> +#define CONFIG_SYS_HZ 1000
> +
> +#include <asm/arch/imx-regs.h>
> +
> +#define CONFIG_DISPLAY_CPUINFO
> +#define CONFIG_BOARD_EARLY_INIT_F
> +#define CONFIG_REVISION_TAG
> +#define CONFIG_SYS_NO_FLASH
> +
> +/*
> + * U-Boot Commands
> + */
> +#include <config_cmd_default.h>
> +#define CONFIG_DISPLAY_BOARDINFO
> +#define CONFIG_DOS_PARTITION
> +
> +#define CONFIG_CMD_DATE
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_EXT2
> +#define CONFIG_CMD_FAT
> +#define CONFIG_CMD_I2C
> +#define CONFIG_CMD_MII
> +#define CONFIG_CMD_MMC
> +#define CONFIG_CMD_NAND
> +#define CONFIG_CMD_NET
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_SATA
> +#define CONFIG_CMD_USB
> +
> +/*
> + * Memory configurations
> + */
> +#define CONFIG_NR_DRAM_BANKS 2
> +#define PHYS_SDRAM_1 CSD0_BASE_ADDR
> +#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
> +#define PHYS_SDRAM_2 CSD1_BASE_ADDR
> +#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024)
> +#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
> +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
> +#define CONFIG_SYS_MEMTEST_START 0x70000000
> +#define CONFIG_SYS_MEMTEST_END 0xaff00000
> +
> +#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
> +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
> +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
> +
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_ADDR \
> + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +#define CONFIG_SYS_TEXT_BASE 0x71000000
> +
> +/*
> + * U-Boot general configurations
> + */
> +#define CONFIG_SYS_LONGHELP
> +#define CONFIG_SYS_PROMPT "=> "
> +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
> +#define CONFIG_SYS_PBSIZE \
> + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
> + /* Print buffer size */
> +#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> + /* Boot argument buffer size */
> +#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
> +#define CONFIG_AUTO_COMPLETE /* Command auto complete */
> +#define CONFIG_CMDLINE_EDITING /* Command history etc */
> +#define CONFIG_SYS_HUSH_PARSER
> +
> +/*
> + * Serial Driver
> + */
> +#define CONFIG_MXC_UART
> +#define CONFIG_MXC_UART_BASE UART2_BASE
> +#define CONFIG_CONS_INDEX 1
> +#define CONFIG_BAUDRATE 115200
> +
> +/*
> + * MMC Driver
> + */
> +#ifdef CONFIG_CMD_MMC
> +#define CONFIG_MMC
> +#define CONFIG_GENERIC_MMC
> +#define CONFIG_FSL_ESDHC
> +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
> +#define CONFIG_SYS_FSL_ESDHC_NUM 1
> +#endif
> +
> +/*
> + * NAND
> + */
> +#define CONFIG_ENV_SIZE (16 * 1024)
> +#ifdef CONFIG_CMD_NAND
> +#define CONFIG_SYS_MAX_NAND_DEVICE 1
> +#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI
> +#define CONFIG_NAND_MXC
> +#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
> +#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
> +#define CONFIG_SYS_NAND_LARGEPAGE
> +#define CONFIG_MXC_NAND_HWECC
> +#define CONFIG_SYS_NAND_USE_FLASH_BBT
> +
> +/* Environment is in NAND */
> +#define CONFIG_ENV_IS_IN_NAND
> +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
> +#define CONFIG_ENV_SECT_SIZE (128 * 1024)
> +#define CONFIG_ENV_RANGE (512 * 1024)
> +#define CONFIG_ENV_OFFSET 0x100000
> +#define CONFIG_ENV_OFFSET_REDUND \
> + (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
> +
> +#define CONFIG_CMD_UBI
> +#define CONFIG_CMD_UBIFS
> +#define CONFIG_CMD_MTDPARTS
> +#define CONFIG_RBTREE
> +#define CONFIG_LZO
> +#define CONFIG_MTD_DEVICE
> +#define CONFIG_MTD_PARTITIONS
> +#define MTDIDS_DEFAULT "nand0=mxc-nand"
> +#define MTDPARTS_DEFAULT \
> + "mtdparts=mxc-nand:" \
> + "1m(bootloader)ro," \
> + "512k(environment)," \
> + "512k(redundant-environment)," \
> + "4m(kernel)," \
> + "128k(fdt)," \
> + "8m(ramdisk)," \
> + "-(filesystem)"
> +#else
> +#define CONFIG_ENV_IS_NOWHERE
> +#endif
> +
> +/*
> + * Ethernet on SOC (FEC)
> + */
> +#ifdef CONFIG_CMD_NET
> +#define CONFIG_FEC_MXC
> +#define IMX_FEC_BASE FEC_BASE_ADDR
> +#define CONFIG_FEC_MXC_PHYADDR 0x0
> +#define CONFIG_MII
> +#define CONFIG_DISCOVER_PHY
> +#define CONFIG_FEC_XCV_TYPE RMII
> +#define CONFIG_PHYLIB
> +#define CONFIG_PHY_MICREL
> +#endif
> +
> +/*
> + * I2C
> + */
> +#ifdef CONFIG_CMD_I2C
> +#define CONFIG_HARD_I2C
> +#define CONFIG_I2C_MXC
> +#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR
> +#define CONFIG_SYS_I2C_SPEED 100000
> +#endif
> +
> +/*
> + * RTC
> + */
> +#ifdef CONFIG_CMD_DATE
> +#define CONFIG_RTC_M41T62
> +#define CONFIG_SYS_I2C_RTC_ADDR 0x68
> +#define CONFIG_SYS_M41T11_BASE_YEAR 2000
> +#endif
> +
> +/*
> + * USB
> + */
> +#ifdef CONFIG_CMD_USB
> +#define CONFIG_USB_EHCI
> +#define CONFIG_USB_EHCI_MX5
> +#define CONFIG_USB_STORAGE
> +#define CONFIG_USB_HOST_ETHER
> +#define CONFIG_USB_ETHER_ASIX
> +#define CONFIG_USB_ETHER_SMSC95XX
> +#define CONFIG_MXC_USB_PORT 1
> +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
> +#define CONFIG_MXC_USB_FLAGS 0
> +#endif
> +
> +/*
> + * SATA
> + */
> +#ifdef CONFIG_CMD_SATA
> +#define CONFIG_DWC_AHSATA
> +#define CONFIG_SYS_SATA_MAX_DEVICE 1
> +#define CONFIG_DWC_AHSATA_PORT_ID 0
> +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
> +#define CONFIG_LBA48
> +#define CONFIG_LIBATA
> +#endif
> +
> +/*
> + * Boot Linux
> + */
> +#define CONFIG_CMDLINE_TAG
> +#define CONFIG_INITRD_TAG
> +#define CONFIG_SETUP_MEMORY_TAGS
> +#define CONFIG_BOOTDELAY 3
> +#define CONFIG_BOOTFILE "m53evk/uImage"
> +#define CONFIG_BOOTARGS "console=ttymxc1,115200"
> +#define CONFIG_LOADADDR 0x70800000
> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> +#define CONFIG_OF_LIBFDT
> +
> +/*
> + * NAND SPL
> + */
> +#define CONFIG_SPL
> +#define CONFIG_SPL_FRAMEWORK
> +#define CONFIG_SPL_TARGET "u-boot-with-nand-spl.imx"
> +#define CONFIG_SPL_BOARD_INIT
> +#define CONFIG_SPL_TEXT_BASE 0x70008000
> +#define CONFIG_SPL_PAD_TO 0x8000
> +#define CONFIG_SPL_STACK 0x70004000
> +#define CONFIG_SPL_GPIO_SUPPORT
> +#define CONFIG_SPL_LIBCOMMON_SUPPORT
> +#define CONFIG_SPL_LIBGENERIC_SUPPORT
> +#define CONFIG_SPL_NAND_SUPPORT
> +#define CONFIG_SPL_SERIAL_SUPPORT
> +
> +#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
> +#define CONFIG_SYS_NAND_PAGE_SIZE 2048
> +#define CONFIG_SYS_NAND_OOBSIZE 64
> +#define CONFIG_SYS_NAND_PAGE_COUNT 64
> +#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
> +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
> +
> +#endif /* __M53EVK_CONFIG_H__ */
> --
> 1.7.10.4
And 1 to 5/6 are fine with me.
Best regards,
Benoît
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