[U-Boot] [PATCH v4 02/10] imx: Add useful fuse definitions

[Benoît Thébaudeau]

Define the UID (SoC unique ID) fuses, and the fuses available for the user.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau at advansee.com>
---
Changes in v4:
 - Add i.MX6 UID.

Changes in v3:
 - Add i.MX6 GP2.

Changes in v2:
 - Rebase against latest master.

 arch/arm/include/asm/arch-mx25/imx-regs.h |   11 ++++++++++-
 arch/arm/include/asm/arch-mx31/imx-regs.h |   12 ++++++++++++
 arch/arm/include/asm/arch-mx35/imx-regs.h |   12 ++++++++++++
 arch/arm/include/asm/arch-mx5/imx-regs.h  |   16 +++++++++++++++-
 arch/arm/include/asm/arch-mx6/imx-regs.h  |   13 ++++++++++++-
 5 files changed, 61 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h
index 99c32d4..cf7bb5a 100644
--- a/arch/arm/include/asm/arch-mx25/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx25/imx-regs.h
@@ -126,10 +126,19 @@ struct iim_regs {
 };
 
 struct fuse_bank0_regs {
-	u32 fuse0_25[0x1a];
+	u32 fuse0_7[8];
+	u32 uid[8];
+	u32 fuse16_25[0xa];
 	u32 mac_addr[6];
 };
 
+struct fuse_bank1_regs {
+	u32 fuse0_21[0x16];
+	u32 usr5;
+	u32 fuse23_29[7];
+	u32 usr6[2];
+};
+
 /* Multi-Layer AHB Crossbar Switch (MAX) registers */
 struct max_regs {
 	u32 mpr0;
diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
index f67f49c..5d8d8f4 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -92,6 +92,18 @@ struct iim_regs {
 	} bank[3];
 };
 
+struct fuse_bank0_regs {
+	u32 fuse0_5[6];
+	u32 usr;
+	u32 fuse7_15[9];
+};
+
+struct fuse_bank2_regs {
+	u32 fuse0;
+	u32 uid[8];
+	u32 fuse9_15[7];
+};
+
 struct iomuxc_regs {
 	u32 unused1;
 	u32 unused2;
diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h
index 64546d2..63c6e24 100644
--- a/arch/arm/include/asm/arch-mx35/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx35/imx-regs.h
@@ -274,6 +274,18 @@ struct iim_regs {
 	} bank[3];
 };
 
+struct fuse_bank0_regs {
+	u32 fuse0_7[8];
+	u32 uid[8];
+	u32 fuse16_31[0x10];
+};
+
+struct fuse_bank1_regs {
+	u32 fuse0_21[0x16];
+	u32 usr;
+	u32 fuse23_31[9];
+};
+
 /* General Purpose Timer (GPT) registers */
 struct gpt_regs {
 	u32 ctrl;	/* control */
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index b237d5f..559547c 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -516,8 +516,14 @@ struct iim_regs {
 };
 
 struct fuse_bank0_regs {
-	u32	fuse0_23[24];
+	u32	fuse0_7[8];
+	u32	uid[8];
+	u32	fuse16_23[8];
+#if defined(CONFIG_MX51)
+	u32	imei[8];
+#elif defined(CONFIG_MX53)
 	u32	gp[8];
+#endif
 };
 
 struct fuse_bank1_regs {
@@ -526,6 +532,14 @@ struct fuse_bank1_regs {
 	u32	fuse15_31[0x11];
 };
 
+#if defined(CONFIG_MX53)
+struct fuse_bank4_regs {
+	u32	fuse0_4[5];
+	u32	gp[3];
+	u32	fuse8_31[0x18];
+};
+#endif
+
 #endif /* __ASSEMBLER__*/
 
 #endif				/* __ASM_ARCH_MX5_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 680e752..03abb2a 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -462,6 +462,15 @@ struct ocotp_regs {
 	} bank[16];
 };
 
+struct fuse_bank0_regs {
+	u32	lock;
+	u32	rsvd0[3];
+	u32	uid_low;
+	u32	rsvd1[3];
+	u32	uid_high;
+	u32	rsvd2[0x17];
+};
+
 struct fuse_bank4_regs {
 	u32	sjc_resp_low;
 	u32     rsvd0[3];
@@ -472,7 +481,9 @@ struct fuse_bank4_regs {
 	u32     mac_addr_high;
 	u32	rsvd3[0xb];
 	u32	gp1;
-	u32	rsvd4[7];
+	u32	rsvd4[3];
+	u32	gp2;
+	u32	rsvd5[3];
 };
 
 struct aipstz_regs {
-- 
1.7.10.4