[U-Boot] [PATCH v2 08/15] sf: Respect maximum SPI write size

[Jagan Teki]

Hi Simon,

On Mon, Mar 11, 2013 at 9:38 PM, Simon Glass <sjg at chromium.org> wrote:
> Some SPI flash controllers (e.g. Intel ICH) have a limit on the number of
> bytes that can be in a write transaction. Support this by breaking the
> writes into multiple transactions.
>
> Signed-off-by: Simon Glass <sjg at chromium.org>
> ---
> Changes in v2: None
>
>  drivers/mtd/spi/spi_flash.c | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
> index 17f3d3c..b82011d 100644
> --- a/drivers/mtd/spi/spi_flash.c
> +++ b/drivers/mtd/spi/spi_flash.c
> @@ -87,6 +87,9 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset,
>         for (actual = 0; actual < len; actual += chunk_len) {
>                 chunk_len = min(len - actual, page_size - byte_addr);
>
> +               if (flash->spi->max_write_size)
> +                       chunk_len = min(chunk_len, flash->spi->max_write_size);
> +
>                 cmd[1] = page_addr >> 8;
>                 cmd[2] = page_addr;
>                 cmd[3] = byte_addr;
> @@ -111,8 +114,11 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset,
>                 if (ret)
>                         break;
>
> -               page_addr++;
> -               byte_addr = 0;
> +               byte_addr += chunk_len;
> +               if (byte_addr == page_size) {
> +                       page_addr++;
> +                       byte_addr = 0;
> +               }

Does this change required to handle < page_size writes, means if the
user is giving an offset other than
multiples of page_sizes?

Thanks,
Jagan.