[U-Boot] [PATCH v5 3/7] mpc85xx: Add CONFIG_RELEASE_CORE0_ONLY

[dirk.eibach at gdsys.cc]

From: Dirk Eibach <eibach at gdsys.de>

If CONFIG_RELEASE_CORE0_ONLY is set, all cores except core0 are kept in
holdoff mode.

Signed-off-by: Dirk Eibach <dirk.eibach at gdsys.cc>
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/powerpc/cpu/mpc85xx/mp.c |    8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index 43d4836..73c1024 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -350,7 +350,11 @@ static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
 	volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
 	u32 devdisr;
 	int timeout = 10;
+	int numcores = 1;
 
+#ifndef CONFIG_RELEASE_CORE0_ONLY
+	numcores = cpu_numcores();
+#endif
 	whoami = in_be32(&pic->whoami);
 	out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12));
 
@@ -363,7 +367,7 @@ static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
 	out_be32(&gur->devdisr, devdisr);
 
 	/* release the hounds */
-	up = ((1 << cpu_numcores()) - 1);
+	up = ((1 << numcores) - 1);
 	bpcr = in_be32(&ecm->eebpcr);
 	bpcr |= (up << 24);
 	out_be32(&ecm->eebpcr, bpcr);
@@ -373,7 +377,7 @@ static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
 	/* wait for everyone */
 	while (timeout) {
 		int i;
-		for (i = 0; i < cpu_numcores(); i++) {
+		for (i = 0; i < numcores; i++) {
 			if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
 				cpu_up_mask |= (1 << i);
 		};
-- 
1.7.2.5