[U-Boot] [PATCH] drivers/block/systemace: fixes read/write words for bus width = 8

[Michal Simek]

Hi Wolfgang,

2013/1/2 Wolfgang Denk <wd at denx.de>:
> Dear Alexey Brodkin,
>
> In message <1357137512-8618-1-git-send-email-alexey.brodkin at gmail.com> you wrote:
>> From: Alexey Brodkin <abrodkin at synopsys.com>
>>
>> Current implementation works fine for bus width = 16 bits because we
>> never get into "if" branch.
>>
>> If one sets width to 8 bits there will be 2 consequent data accesses
>> (read/write):
>> 1. Correct data access for 8-bit bus
>> 2. Unconditional (and in this case incorrect) data access as if data bus
>> is 16-bit wide
>
> Sorry, I don't get this.
>
> You say, if one sets width to 8 bits, then the code fails when the bus
> is actually 16 bits wide?
>
> But this is just a bad configuration then - why do we need to change
> the code?  All that is needed is to run with a correct configuration?

Here is that function with my comment about missing "else".
In ace_writew function we shouldn't write 16bit value when width is 8.
(It probably doesn't break anything but it is not correct - I will
check it on the HW)

static void ace_writew(u16 val, unsigned off)
{
	if (width == 8) {
#if !defined(__BIG_ENDIAN)
		writeb(val >> 8, base + off);
		writeb(val, base + off + 1);
#else
		writeb(val, base + off);
		writeb(val >> 8, base + off + 1);
#endif
	}

<----------------------- missing else here
	writew(base + off, val);
}

For ace_readw is situation different because it always returns value for width 8
that's why it never reach 16bit read.

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian