[U-Boot] [PATCH] powerpc/p2041: skip waiting for SERDES bank 3 reset done

Anatolij Gustschin agust at denx.de
Wed Jan 23 11:36:44 CET 2013


Hello,

On Wed, 23 Jan 2013 10:17:44 +0000
Xie Shaohui-B21989 <B21989 at freescale.com> wrote:

> Hello, Anatolij Gustschin,
> 
> Could you please post the " bank 3 reset wait timeout" dumped by U-boot,
> I don't see this, and also the RCW dump?

currently I do not have access to the p2041rdb board, but here is the
previously captured boot log where I've seen this:


U-Boot 2011.09-00000-g2c02d1d (Oct 22 2011 - 18:31:36)

CPU0:  P2041E, Version: 1.0, (0x82180110)
Core:  E500MC, Version: 2.2, (0x80230022)
Clock Configuration:
       CPU0:1500 MHz, CPU1:1500 MHz, CPU2:1500 MHz, CPU3:1500 MHz,
       CCB:750  MHz,
       DDR:666.667 MHz (1333.333 MT/s data rate) (Asynchronous), LBC:93.750 MHz
       FMAN1: 583.333 MHz
       PME:   375 MHz
L1:    D-cache 32 kB enabled
       I-cache 32 kB enabled
Board: P2041RDB, CPLD version: 4.0 vBank: 0
36-bit Addressing
Reset Configuration Word (RCW):
       00000000: 12600000 00000000 241c0000 00000000
       00000010: 249f40c0 c3c02000 fe800000 40000000
       00000020: 00000000 00000000 00000000 d0030f07
       00000030: 00000000 00000000 00000000 00000000
SERDES Reference Clocks: Bank1=100Mhz Bank2=125Mhz
I2C:   ready
SPI:   ready
DRAM:  Initializing....using SPD
Detected UDIMM UG51U6400N8SU-ACF
2 GiB left unmapped
4 GiB (DDR3, 64-bit, CL=9, ECC off)
       DDR Chip-Select Interleaving Mode: CS0+CS1
Testing 0x00000000 - 0x7fffffff
Testing 0x80000000 - 0xffffffff
Remap DDR 2 GiB left unmapped

POST memory PASSED
Flash: 128 MiB
L2:    128 KB enabled
Corenet Platform Cache: 1024 KB enabled
SERDES: timeout resetting bank 3
SRIO1: disabled
SRIO2: disabled
MMC:  FSL_ESDHC: 0
EEPROM: Invalid ID (ff ff ff ff)
PCIe1: disabled
PCIe2: Root Complex, no link, regs @ 0xfe201000
PCIe2: Bus 00 - 00
PCIe3: disabled
In:    serial
Out:   serial
Err:   serial
Net:   Initializing Fman
Fman1: DTSEC3 set to unknown interface 11
Fman1: Uploading microcode version 101.8.0
PHY reset timed out
FM1 at DTSEC1, FM1 at DTSEC2, FM1 at DTSEC4, FM1 at DTSEC5, FM1 at TGEC1
Hit any key to stop autoboot:  0


Thanks,

Anatolij


More information about the U-Boot mailing list