[U-Boot] [PATCH v3 2/7] mx23evk: Fix DDR pin iomux settings

[Marek Vasut]

Dear Fabio Estevam,

> On Thu, May 2, 2013 at 11:37 PM, Marek Vasut <marex at denx.de> wrote:
> > Uh, why is it even set ? Does the bootrom screw up with it? But then it's
> > cool, just fix those few remaining ramblings of mine and stick my Acks
> > on it.
> 
> Ok, let's go step by step.
> 
> mx23 reference manual says that EMI pins voltage bits can be:
> 0 - for normal operation
> 1  - invalid.
> 
> After reset this bit is 1 and the iomux driver needs to clear this bit.
> 
> Let's look at the defines:
> 
> #define MXS_PAD_1V8	((PAD_1V8 << MXS_PAD_VOL_SHIFT) | \
> 					MXS_PAD_VOL_VALID_MASK)
> #define MXS_PAD_3V3	((PAD_3V3 << MXS_PAD_VOL_SHIFT) | \
> 					MXS_PAD_VOL_VALID_MASK)
> 
> and then in the iomux;c driver:
> 
> 	if (PAD_VOL_VALID(pad)) {
> 		bp = PAD_PIN(pad) % 8 * 4 + 2;
> 		mxs_reg = (struct mxs_register_32 *)(iomux_base + ofs);
> 		if (PAD_VOL(pad))
> 			writel(1 << bp, &mxs_reg->reg_set);
> 		else
> 			writel(1 << bp, &mxs_reg->reg_clr);
> 	}
> 
> So the only way that the iomux driver can clear the voltage bit is if
> PAD_VOL_VALID(pad) is true, and the only way that PAD_VOL_VALID(pad)
> can be true is if either MXS_PAD_3V3 or MXS_PAD_1V8 are defined, since
> they have the MXS_PAD_VOL_VALID_MASK bit in their definitions.

Yuck. But then, why not configure the pins as 1V8 ? But either way WFM.

Best regards,
Marek Vasut