1. Applied on latest mpc85xx u-boot git tree: git://www.denx.de/git/u-boot-mpc85xx.git
2. Tested on T4240QDS and P1010RDB board.
> -----Original Message-----
> From: Hu Mingkai-B21284
> Sent: Thursday, May 16, 2013 10:18 AM
> To: u-boot at lists.denx.de
> Cc: Fleming Andy-AFLEMING; sun york-R58495; Hu Mingkai-B21284
> Subject: [PATCH v2] fsl_ifc: add support for different IFC bank count
>
> From: Mingkai Hu <Mingkai.hu at freescale.com>
>
> Calculate reserved fields according to IFC bank count
>
> 1. Move csor_ext register behind csor register and fix res offset 2. Move
> ifc bank count to config_mpc85xx.h to support 8 bank count 3. Guard
> fsl_ifc.h with CONFIG_FSL_IFC macro to eliminate the compile
> error on some devices that does not have IFC controller.
>
> Signed-off-by: Mingkai Hu <Mingkai.hu at freescale.com>
> ---
> arch/powerpc/cpu/mpc8xxx/fsl_ifc.c | 58 ++++++++++++++++++-
> arch/powerpc/include/asm/config_mpc85xx.h | 7 +++
> arch/powerpc/include/asm/fsl_ifc.h | 95 +++++++++++++++++++++----
> ------
> 3 files changed, 128 insertions(+), 32 deletions(-)
>
> diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
> b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
> index 56b319f..f0da355 100644
> --- a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
> +++ b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
> @@ -26,7 +26,7 @@ void print_ifc_regs(void)
> int i, j;
>
> printf("IFC Controller Registers\n");
> - for (i = 0; i < FSL_IFC_BANK_COUNT; i++) {
> + for (i = 0; i < CONFIG_SYS_FSL_IFC_BANK_COUNT; i++) {
> printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n",
> i, get_ifc_cspr(i), i, get_ifc_amask(i),
> i, get_ifc_csor(i));
> @@ -94,4 +94,60 @@ void init_early_memctl_regs(void)
> set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
> set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3); #endif
> +
> +#ifdef CONFIG_SYS_CSPR4_EXT
> + set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT); #endif #if
> +defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4)
> + set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0);
> + set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1);
> + set_ifc_ftim(IFC_CS4, IFC_FTIM2, CONFIG_SYS_CS4_FTIM2);
> + set_ifc_ftim(IFC_CS4, IFC_FTIM3, CONFIG_SYS_CS4_FTIM3);
> +
> + set_ifc_cspr(IFC_CS4, CONFIG_SYS_CSPR4);
> + set_ifc_amask(IFC_CS4, CONFIG_SYS_AMASK4);
> + set_ifc_csor(IFC_CS4, CONFIG_SYS_CSOR4); #endif
> +
> +#ifdef CONFIG_SYS_CSPR5_EXT
> + set_ifc_cspr_ext(IFC_CS5, CONFIG_SYS_CSPR5_EXT); #endif #if
> +defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5)
> + set_ifc_ftim(IFC_CS5, IFC_FTIM0, CONFIG_SYS_CS5_FTIM0);
> + set_ifc_ftim(IFC_CS5, IFC_FTIM1, CONFIG_SYS_CS5_FTIM1);
> + set_ifc_ftim(IFC_CS5, IFC_FTIM2, CONFIG_SYS_CS5_FTIM2);
> + set_ifc_ftim(IFC_CS5, IFC_FTIM3, CONFIG_SYS_CS5_FTIM3);
> +
> + set_ifc_cspr(IFC_CS5, CONFIG_SYS_CSPR5);
> + set_ifc_amask(IFC_CS5, CONFIG_SYS_AMASK5);
> + set_ifc_csor(IFC_CS5, CONFIG_SYS_CSOR5); #endif
> +
> +#ifdef CONFIG_SYS_CSPR6_EXT
> + set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT); #endif #if
> +defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6)
> + set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0);
> + set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1);
> + set_ifc_ftim(IFC_CS6, IFC_FTIM2, CONFIG_SYS_CS6_FTIM2);
> + set_ifc_ftim(IFC_CS6, IFC_FTIM3, CONFIG_SYS_CS6_FTIM3);
> +
> + set_ifc_cspr(IFC_CS6, CONFIG_SYS_CSPR6);
> + set_ifc_amask(IFC_CS6, CONFIG_SYS_AMASK6);
> + set_ifc_csor(IFC_CS6, CONFIG_SYS_CSOR6); #endif
> +
> +#ifdef CONFIG_SYS_CSPR7_EXT
> + set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT); #endif #if
> +defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7)
> + set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0);
> + set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1);
> + set_ifc_ftim(IFC_CS7, IFC_FTIM2, CONFIG_SYS_CS7_FTIM2);
> + set_ifc_ftim(IFC_CS7, IFC_FTIM3, CONFIG_SYS_CS7_FTIM3);
> +
> + set_ifc_cspr(IFC_CS7, CONFIG_SYS_CSPR7);
> + set_ifc_amask(IFC_CS7, CONFIG_SYS_AMASK7);
> + set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7); #endif
> }
> diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
> b/arch/powerpc/include/asm/config_mpc85xx.h
> index 68ca871..1601c72 100644
> --- a/arch/powerpc/include/asm/config_mpc85xx.h
> +++ b/arch/powerpc/include/asm/config_mpc85xx.h
> @@ -139,6 +139,7 @@
> #define CONFIG_SYS_FSL_SEC_COMPAT 4
> #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
> #define CONFIG_NUM_DDR_CONTROLLERS 1
> +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
> #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
> #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
> #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
> @@ -494,6 +495,7 @@
> #define CONFIG_TSECV2
> #define CONFIG_SYS_FSL_SEC_COMPAT 4
> #define CONFIG_NUM_DDR_CONTROLLERS 1
> +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
> #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
> #define CONFIG_NAND_FSL_IFC
> #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -506,6 +508,7 @@ #define
> CONFIG_TSECV2
> #define CONFIG_SYS_FSL_SEC_COMPAT 4
> #define CONFIG_NUM_DDR_CONTROLLERS 2
> +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
> #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
> #define CONFIG_NAND_FSL_IFC
> #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -530,6 +533,7 @@
> #define CONFIG_SYS_NUM_FM2_10GEC 2
> #define CONFIG_NUM_DDR_CONTROLLERS 3
> #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
> +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
> #define CONFIG_SYS_FMAN_V3
> #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
> #define CONFIG_SYS_FSL_TBCLK_DIV 16
> @@ -563,6 +567,7 @@
> #define CONFIG_SYS_NUM_FM2_10GEC 1
> #define CONFIG_NUM_DDR_CONTROLLERS 2
> #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
> +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
> #define CONFIG_SYS_FMAN_V3
> #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
> #define CONFIG_SYS_FSL_TBCLK_DIV 16
> @@ -591,6 +596,7 @@
> #define CONFIG_SYS_NUM_FM1_DTSEC 4
> #define CONFIG_NUM_DDR_CONTROLLERS 1
> #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
> +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
> #define CONFIG_SYS_FMAN_V3
> #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
> #define CONFIG_SYS_FSL_TBCLK_DIV 16
> @@ -614,6 +620,7 @@
> #define CONFIG_SYS_NUM_FM1_10GEC 2
> #define CONFIG_NUM_DDR_CONTROLLERS 2
> #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
> +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
> #define CONFIG_SYS_FMAN_V3
> #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
> #define CONFIG_SYS_FSL_TBCLK_DIV 16
> diff --git a/arch/powerpc/include/asm/fsl_ifc.h
> b/arch/powerpc/include/asm/fsl_ifc.h
> index ba41b73..3baf4cc 100644
> --- a/arch/powerpc/include/asm/fsl_ifc.h
> +++ b/arch/powerpc/include/asm/fsl_ifc.h
> @@ -21,6 +21,7 @@
> #ifndef __ASM_PPC_FSL_IFC_H
> #define __ASM_PPC_FSL_IFC_H
>
> +#ifdef CONFIG_FSL_IFC
> #include <config.h>
> #include <common.h>
>
> @@ -798,13 +799,15 @@ extern void init_early_memctl_regs(void); #define
> set_ifc_ftim(i, j, v) \
> (out_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v))
>
> -#define FSL_IFC_BANK_COUNT 4
> -
> enum ifc_chip_sel {
> IFC_CS0,
> IFC_CS1,
> IFC_CS2,
> IFC_CS3,
> + IFC_CS4,
> + IFC_CS5,
> + IFC_CS6,
> + IFC_CS7,
> };
>
> enum ifc_ftims {
> @@ -907,6 +910,49 @@ struct fsl_ifc_gpcm {
> u32 res4[0x1F3];
> };
>
> +#ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT
> +#if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8)
> +#define IFC_CSPR_REG_LEN 148
> +#define IFC_AMASK_REG_LEN 144
> +#define IFC_CSOR_REG_LEN 144
> +#define IFC_FTIM_REG_LEN 576
> +
> +#define IFC_CSPR_USED_LEN sizeof(struct fsl_ifc_cspr) * \
> + CONFIG_SYS_FSL_IFC_BANK_COUNT
> +#define IFC_AMASK_USED_LEN sizeof(struct fsl_ifc_amask) * \
> + CONFIG_SYS_FSL_IFC_BANK_COUNT
> +#define IFC_CSOR_USED_LEN sizeof(struct fsl_ifc_csor) * \
> + CONFIG_SYS_FSL_IFC_BANK_COUNT
> +#define IFC_FTIM_USED_LEN sizeof(struct fsl_ifc_ftim) * \
> + CONFIG_SYS_FSL_IFC_BANK_COUNT
> +#else
> +#error IFC BANK count not vaild
> +#endif
> +#else
> +#error IFC BANK count not defined
> +#endif
> +
> +struct fsl_ifc_cspr {
> + u32 cspr_ext;
> + u32 cspr;
> + u32 res;
> +};
> +
> +struct fsl_ifc_amask {
> + u32 amask;
> + u32 res[0x2];
> +};
> +
> +struct fsl_ifc_csor {
> + u32 csor;
> + u32 csor_ext;
> + u32 res;
> +};
> +
> +struct fsl_ifc_ftim {
> + u32 ftim[4];
> + u32 res[0x8];
> +};
>
> /*
> * IFC Controller Registers
> @@ -914,44 +960,30 @@ struct fsl_ifc_gpcm { struct fsl_ifc {
> u32 ifc_rev;
> u32 res1[0x2];
> - struct {
> - u32 cspr_ext;
> - u32 cspr;
> - u32 res2;
> - } cspr_cs[FSL_IFC_BANK_COUNT];
> - u32 res3[0x19];
> - struct {
> - u32 amask;
> - u32 res4[0x2];
> - } amask_cs[FSL_IFC_BANK_COUNT];
> - u32 res5[0x17];
> - struct {
> - u32 csor_ext;
> - u32 csor;
> - u32 res6;
> - } csor_cs[FSL_IFC_BANK_COUNT];
> - u32 res7[0x19];
> - struct {
> - u32 ftim[4];
> - u32 res8[0x8];
> - } ftim_cs[FSL_IFC_BANK_COUNT];
> - u32 res9[0x60];
> + struct fsl_ifc_cspr cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
> + u8 res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN];
> + struct fsl_ifc_amask amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
> + u8 res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN];
> + struct fsl_ifc_csor csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
> + u8 res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN];
> + struct fsl_ifc_ftim ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
> + u8 res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN];
> u32 rb_stat;
> - u32 res10[0x2];
> + u32 res6[0x2];
> u32 ifc_gcr;
> - u32 res11[0x2];
> + u32 res7[0x2];
> u32 cm_evter_stat;
> - u32 res12[0x2];
> + u32 res8[0x2];
> u32 cm_evter_en;
> - u32 res13[0x2];
> + u32 res9[0x2];
> u32 cm_evter_intr_en;
> - u32 res14[0x2];
> + u32 res10[0x2];
> u32 cm_erattr0;
> u32 cm_erattr1;
> - u32 res15[0x2];
> + u32 res11[0x2];
> u32 ifc_ccr;
> u32 ifc_csr;
> - u32 res16[0x2EB];
> + u32 res12[0x2EB];
> struct fsl_ifc_nand ifc_nand;
> struct fsl_ifc_nor ifc_nor;
> struct fsl_ifc_gpcm ifc_gpcm;
> @@ -961,6 +993,7 @@ struct fsl_ifc {
> #undef CSPR_MSEL_NOR
> #define CSPR_MSEL_NOR CSPR_MSEL_GPCM
> #endif
> +#endif /* CONFIG_FSL_IFC */
>
> #endif /* __ASSEMBLY__ */
> #endif /* __ASM_PPC_FSL_IFC_H */
> --
> 1.8.0