[U-Boot] [PATCH] arm: pxa: PXA270 D-Cache as ram
Marek Vasut
marex at denx.de
Tue May 21 17:00:20 CEST 2013
Dear Sergey Yanovich,
> Dear Marek Vasut,
>
> On Tue, 2013-05-21 at 13:38 +0200, Marek Vasut wrote:
> > Yes, it's just an in-CPU RAM.
>
> Well, it is not 'just' RAM. It preserves its state during deep sleep and
> power off modes.
So does RAM during sleep state ;-)
> > > Anyway, SRAM preserves its state when power is off. Poweroff time could
> > > be in years with a backup battery. In addition, D-Cache is an order of
> > > magnitude faster than SRAM (approx. 9 times) for both reads and writes.
> >
> > Is there any measurable difference between using DCache and SRAM? Do you
> > have any evidence that a speedup happens?
>
> I haven't done any special profiling. I am just relying on PXA270 EMTS
> table 6-14. The table says SRAM reads take 9 cycles, writes take 7
> cycles. D-Cache operations take 1 cycle.
>
> > Still, the SRAM/DCache is only used until you leave board_init_f(), then
> > it's all DRAM.
>
> Yes, the patch as it is will only affects relocation speed and preserve
> SRAM from corruption.
Now this is the right (convincing) argument! What kind of corruption ? When does
it occur ?
> The speed gain can also be applied to uImage
> copying/unpacking, but that requires deeper understanding than I have at
> the moment.
Uh ... I lost you here. Can you please elaborate some more ?
Best regards,
Marek Vasut
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