[U-Boot] enabling ecc on P2041 and QoreIQ familly not valid for memory >= 4GB

[Benoit Sansoni]

Hi ,

I found out an issue when enabling ECC for P2041 platform with an amount
of memory of 8GB.
The routine "void dma_meminit(uint val, uint size)" is not adapted to
manage memory size greater or equal to 4GB due to the 'uint' type.
With this typing the dma_meminit sees 0 as size when memory is for
example at 8GB. So the ECC part of the memory is not initialized and
when going in memory the code crash.
To correct it you need to use phys_size_t type instead of uint.
It is the same thing for all routines that are called by "dma_meminit".
I attached a patch that able to correct it easily.
This patch should be integrated in the main branch I think so.

Regards,
Benoit

diff -u vx3240/u-boot-2012.10/arch/powerpc/include/asm/fsl_ddr_sdram.h:1.1.1.1 vx3240/u-boot-2012.10/arch/powerpc/include/asm/fsl_ddr_sdram.h:1.2
--- vx3240/u-boot-2012.10/arch/powerpc/include/asm/fsl_ddr_sdram.h:1.1.1.1	Tue Jan  8 10:23:37 2013
+++ vx3240/u-boot-2012.10/arch/powerpc/include/asm/fsl_ddr_sdram.h	Fri Jul 18 10:31:22 2014
@@ -308,7 +308,7 @@
  #endif
  
  #if defined(CONFIG_DDR_ECC)
-extern void ddr_enable_ecc(unsigned int dram_size);
+extern void ddr_enable_ecc(phys_size_t dram_size);
  #endif
  
diff -u vx3240/u-boot-2012.10/arch/powerpc/include/asm/fsl_dma.h:1.1.1.1 vx3240/u-boot-2012.10/arch/powerpc/include/asm/fsl_dma.h:1.2
--- vx3240/u-boot-2012.10/arch/powerpc/include/asm/fsl_dma.h:1.1.1.1	Tue Jan  8 10:23:37 2013
+++ vx3240/u-boot-2012.10/arch/powerpc/include/asm/fsl_dma.h	Fri Jul 18 10:31:22 2014
@@ -134,7 +134,7 @@
  void dma_init(void);
  int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t n);
  #if (defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
-void dma_meminit(uint val, uint size);
+void dma_meminit(uint val, phys_size_t size);
  #endif
  #endif
  
diff -u vx3240/u-boot-2012.10/drivers/dma/fsl_dma.c:1.1.1.1 vx3240/u-boot-2012.10/drivers/dma/fsl_dma.c:1.2
--- vx3240/u-boot-2012.10/drivers/dma/fsl_dma.c:1.1.1.1	Tue Jan  8 10:23:55 2013
+++ vx3240/u-boot-2012.10/drivers/dma/fsl_dma.c	Fri Jul 18 14:28:31 2014
@@ -113,14 +113,13 @@
  
  	while (count) {
  		xfer_size = MIN(FSL_DMA_MAX_SIZE, count);
-
  		out_dma32(&dma->dar, (u32) (dest & 0xFFFFFFFF));
  		out_dma32(&dma->sar, (u32) (src & 0xFFFFFFFF));
  #if !defined(CONFIG_MPC83xx)
  		out_dma32(&dma->satr,
-			in_dma32(&dma->satr) | (u32)((u64)src >> 32));
+			in_dma32(&dma->satr) | (u32)(src >> 32));
  		out_dma32(&dma->datr,
-			in_dma32(&dma->datr) | (u32)((u64)dest >> 32));
+			in_dma32(&dma->datr) | (u32)(dest >> 32));
  #endif
  		out_dma32(&dma->bcr, xfer_size);
  		dma_sync();
@@ -152,33 +151,36 @@
  #if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) &&	\
  	!defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) ||		\
  	(defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)))
-void dma_meminit(uint val, uint size)
+void dma_meminit(uint val, phys_size_t size)
  {
-	uint *p = 0;
-	uint i = 0;
-
-	for (*p = 0; p < (uint *)(8 * 1024); p++) {
-		if (((uint)p & 0x1f) == 0)
-			ppcDcbz((ulong)p);
-
-		*p = (uint)CONFIG_MEM_INIT_VALUE;
-
-		if (((uint)p & 0x1c) == 0x1c)
-			ppcDcbf((ulong)p);
-	}
-
-	dmacpy(0x002000, 0, 0x002000); /* 8K */
-	dmacpy(0x004000, 0, 0x004000); /* 16K */
-	dmacpy(0x008000, 0, 0x008000); /* 32K */
-	dmacpy(0x010000, 0, 0x010000); /* 64K */
-	dmacpy(0x020000, 0, 0x020000); /* 128K */
-	dmacpy(0x040000, 0, 0x040000); /* 256K */
-	dmacpy(0x080000, 0, 0x080000); /* 512K */
-	dmacpy(0x100000, 0, 0x100000); /* 1M */
-	dmacpy(0x200000, 0, 0x200000); /* 2M */
-	dmacpy(0x400000, 0, 0x400000); /* 4M */
-
-	for (i = 1; i < size / 0x800000; i++)
-		dmacpy((0x800000 * i), 0, 0x800000);
+  uint *p = 0;
+  u64 i = 0;
+  phys_addr_t addr;
+
+  for (*p = 0; p < (uint *)(8 * 1024); p++) {
+    if (((uint)p & 0x1f) == 0)
+      ppcDcbz((ulong)p);
+
+    *p = (uint)CONFIG_MEM_INIT_VALUE;
+
+    if (((uint)p & 0x1c) == 0x1c)
+      ppcDcbf((ulong)p);
+  }
+
+  dmacpy(0x002000, 0, 0x002000); /* 8K */
+  dmacpy(0x004000, 0, 0x004000); /* 16K */
+  dmacpy(0x008000, 0, 0x008000); /* 32K */
+  dmacpy(0x010000, 0, 0x010000); /* 64K */
+  dmacpy(0x020000, 0, 0x020000); /* 128K */
+  dmacpy(0x040000, 0, 0x040000); /* 256K */
+  dmacpy(0x080000, 0, 0x080000); /* 512K */
+  dmacpy(0x100000, 0, 0x100000); /* 1M */
+  dmacpy(0x200000, 0, 0x200000); /* 2M */
+  dmacpy(0x400000, 0, 0x400000); /* 4M */
+
+  for (i = 1; i < size / 0x800000; i++) {
+    addr = (phys_addr_t) (i * 0x800000);
+    dmacpy(addr, (phys_addr_t)0, 0x800000);
+  }
  }
  #endif