[U-Boot] [PATCH v2 0/3] cadence-quadspi: Fix issues with non 32bit aligned accesses

Goldschmidt Simon sgoldschmidt at de.pepperl-fuchs.com
Wed Jan 10 15:33:35 UTC 2018


On Tue 09/01/18 14:19, Vignesh R wrote:
> This series reverts use of bounce_buf.c for non-DMA related alignment restriction
> and replaces it with local bounce buffer to handle problems with non 32 bit aligned
> writes on TI platforms.
> Based on top of Jason's series:
> https://patchwork.ozlabs.org/cover/856431/
> 
> Tested on K2G EVM.

For this whole series:
Tested on a socfpga-cyclonev board (with a Micron N25QL256A):
Tested-by: Simon Goldschmidt <sgoldschmidt at de.pepperl-fuchs.com>

After applying this series on top of Jason's v5, qspi on the socfpga is finally
working without local fixes!

Regards,
Simon


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