[U-Boot] [PATCH] mmc: fsl_esdhc: Fix i.MX53 eSDHCv3 clock

[Stefano Babic]

Hi Benoît,

On 15/01/2018 00:46, Benoît Thébaudeau wrote:
> Commit 4f425280fa71 ("mmc: fsl_esdhc: Allow all supported prescaler
> values") made it possible to set SYSCTL.SDCLKFS to 0 in SDR mode on
> i.MX, thus bypassing the SD clock frequency prescaler, in order to be
> able to get higher SD clock frequencies in some contexts. However, that
> commit missed the fact that this value is illegal on the eSDHCv3
> instance of the i.MX53. This seems to be the only exception on i.MX,
> this value being legal even for the eSDHCv2 instances of the i.MX53.
> 
> Fix this issue by changing the minimum prescaler value for the single
> instance of the i.MX53 eSDHCv3 controller.
> 
> Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev at gmail.com>
> ---
>  drivers/mmc/fsl_esdhc.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
> index 499d622c6d..90425e8a30 100644
> --- a/drivers/mmc/fsl_esdhc.c
> +++ b/drivers/mmc/fsl_esdhc.c
> @@ -528,14 +528,19 @@ out:
>  
>  static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
>  {
> +	struct fsl_esdhc *regs = priv->esdhc_regs;
>  	int div = 1;
>  #ifdef ARCH_MXC
> +#ifdef CONFIG_MX53
> +	/* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
> +	int pre_div = regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR ? 2 : 1;

It is surely a question of taste - but is it not cleared to surround the
expression with parenthesis ? (regs == .... )


> +#else
>  	int pre_div = 1;
> +#endif
>  #else
>  	int pre_div = 2;
>  #endif
>  	int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
> -	struct fsl_esdhc *regs = priv->esdhc_regs;
>  	int sdhc_clk = priv->sdhc_clk;
>  	uint clk;
>  
> 

Best regards,
Stefano

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