[U-Boot] FW: u-boot v2016 vs v2013

[Fabio Estevam]

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On Thu, Jan 25, 2018 at 9:06 AM, Mehmet Ali İPİN
<mehmet.ipin at pavotek.com.tr> wrote:
> Dear Fabio,
>
> I checked my PHY KSZ9021 schematic  (we used i.mx6 Dual Light) with boundary devices sabre_light_revD(they used i.mx6 quad)  KSZ9021. We both use same clock and data signals on both i.mx6 and PHY sides.
>
> I saw 6.25 MHz clock signal on RGMII_TXCLK pin of i.mx6dl which is connected to the GTX_CLK input pin of PHY same as in sabre light. PHY is multiplying this clock with 5 and generating 31.25 MHz, which is connected back to the ENET_REF_CLK pin of i.mx6dl.
>
> I guess either my global ethernet clock or its pll clock registers or their mask registers are not set correctly, to generate 25 MHz, instead of 6.25 MHz.
>
> May be you know, how may I correct them?

Maybe you need to call enable_fec_anatop_clock() to adjust the FEC clock.