[U-Boot] [PATCH] ARM: dts: uniphier: sync with Linux 5.0-rc2
Masahiro Yamada
yamada.masahiro at socionext.com
Fri Feb 15 00:16:15 UTC 2019
Signed-off-by: Masahiro Yamada <yamada.masahiro at socionext.com>
---
arch/arm/dts/uniphier-ld20.dtsi | 11 ++++-------
arch/arm/dts/uniphier-ld4.dtsi | 14 ++++++++++++++
arch/arm/dts/uniphier-pro4.dtsi | 16 ++++++++++++++++
arch/arm/dts/uniphier-pxs2.dtsi | 6 ++++--
arch/arm/dts/uniphier-sld8.dtsi | 14 ++++++++++++++
5 files changed, 52 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi
index b9ed613..a411f4a 100644
--- a/arch/arm/dts/uniphier-ld20.dtsi
+++ b/arch/arm/dts/uniphier-ld20.dtsi
@@ -206,13 +206,10 @@
cooling-maps {
map0 {
trip = <&cpu_alert>;
- cooling-device = <&cpu0
- THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- map1 {
- trip = <&cpu_alert>;
- cooling-device = <&cpu2
- THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
diff --git a/arch/arm/dts/uniphier-ld4.dtsi b/arch/arm/dts/uniphier-ld4.dtsi
index b73d594..c2706ce 100644
--- a/arch/arm/dts/uniphier-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ld4.dtsi
@@ -235,6 +235,16 @@
};
};
+ dmac: dma-controller at 5a000000 {
+ compatible = "socionext,uniphier-mio-dmac";
+ reg = <0x5a000000 0x1000>;
+ interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
+ <0 71 4>, <0 72 4>, <0 73 4>;
+ clocks = <&mio_clk 7>;
+ resets = <&mio_rst 7>;
+ #dma-cells = <1>;
+ };
+
sd: sdhc at 5a400000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
@@ -246,6 +256,8 @@
clocks = <&mio_clk 0>;
reset-names = "host", "bridge";
resets = <&mio_rst 0>, <&mio_rst 3>;
+ dma-names = "rx-tx";
+ dmas = <&dmac 4>;
bus-width = <4>;
cap-sd-highspeed;
sd-uhs-sdr12;
@@ -263,6 +275,8 @@
clocks = <&mio_clk 1>;
reset-names = "host", "bridge", "hw";
resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
+ dma-names = "rx-tx";
+ dmas = <&dmac 6>;
bus-width = <8>;
cap-mmc-highspeed;
cap-mmc-hw-reset;
diff --git a/arch/arm/dts/uniphier-pro4.dtsi b/arch/arm/dts/uniphier-pro4.dtsi
index ef34208..d090fc7 100644
--- a/arch/arm/dts/uniphier-pro4.dtsi
+++ b/arch/arm/dts/uniphier-pro4.dtsi
@@ -269,6 +269,16 @@
};
};
+ dmac: dma-controller at 5a000000 {
+ compatible = "socionext,uniphier-mio-dmac";
+ reg = <0x5a000000 0x1000>;
+ interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
+ <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>;
+ clocks = <&mio_clk 7>;
+ resets = <&mio_rst 7>;
+ #dma-cells = <1>;
+ };
+
sd: sdhc at 5a400000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
@@ -280,6 +290,8 @@
clocks = <&mio_clk 0>;
reset-names = "host", "bridge";
resets = <&mio_rst 0>, <&mio_rst 3>;
+ dma-names = "rx-tx";
+ dmas = <&dmac 4>;
bus-width = <4>;
cap-sd-highspeed;
sd-uhs-sdr12;
@@ -297,6 +309,8 @@
clocks = <&mio_clk 1>;
reset-names = "host", "bridge", "hw";
resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
+ dma-names = "rx-tx";
+ dmas = <&dmac 5>;
bus-width = <8>;
cap-mmc-highspeed;
cap-mmc-hw-reset;
@@ -313,6 +327,8 @@
clocks = <&mio_clk 2>;
reset-names = "host", "bridge";
resets = <&mio_rst 2>, <&mio_rst 5>;
+ dma-names = "rx-tx";
+ dmas = <&dmac 6>;
bus-width = <4>;
cap-sd-highspeed;
};
diff --git a/arch/arm/dts/uniphier-pxs2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi
index fa25ffd..4e11e85 100644
--- a/arch/arm/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/dts/uniphier-pxs2.dtsi
@@ -141,8 +141,10 @@
cooling-maps {
map {
trip = <&cpu_alert>;
- cooling-device = <&cpu0
- THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
diff --git a/arch/arm/dts/uniphier-sld8.dtsi b/arch/arm/dts/uniphier-sld8.dtsi
index f7fcf6b..efce027 100644
--- a/arch/arm/dts/uniphier-sld8.dtsi
+++ b/arch/arm/dts/uniphier-sld8.dtsi
@@ -239,6 +239,16 @@
};
};
+ dmac: dma-controller at 5a000000 {
+ compatible = "socionext,uniphier-mio-dmac";
+ reg = <0x5a000000 0x1000>;
+ interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
+ <0 71 4>, <0 72 4>, <0 73 4>;
+ clocks = <&mio_clk 7>;
+ resets = <&mio_rst 7>;
+ #dma-cells = <1>;
+ };
+
sd: sdhc at 5a400000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
@@ -250,6 +260,8 @@
clocks = <&mio_clk 0>;
reset-names = "host", "bridge";
resets = <&mio_rst 0>, <&mio_rst 3>;
+ dma-names = "rx-tx";
+ dmas = <&dmac 4>;
bus-width = <4>;
cap-sd-highspeed;
sd-uhs-sdr12;
@@ -267,6 +279,8 @@
clocks = <&mio_clk 1>;
reset-names = "host", "bridge", "hw";
resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
+ dma-names = "rx-tx";
+ dmas = <&dmac 6>;
bus-width = <8>;
cap-mmc-highspeed;
cap-mmc-hw-reset;
--
2.7.4
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