[U-Boot] [PATCH v2 2/8] arm: socfpga: gen5: add reset & sdr node to SPL devicetrees

[Simon Goldschmidt]

The SPL for socfpga gen5 currently takes all peripherals out of reset
unconditionally. To implement proper reset handling for peripherals,
the reset node has to be provided with the SPL dts.

In preparation to move the DDR driver to DM, the sdr node is required
in SPL, too.

This patch adds "u-boot,dm-pre-reloc" to U-Boot specific dtsi addon
files so that the reset manager and SDR driver correctly probe in SPL.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>
---

Changes in v2: None

 arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi          | 8 ++++++++
 arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts             | 8 ++++++++
 arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi | 8 ++++++++
 arch/arm/dts/socfpga_cyclone5_de10_nano.dts            | 8 ++++++++
 arch/arm/dts/socfpga_cyclone5_de1_soc.dts              | 8 ++++++++
 arch/arm/dts/socfpga_cyclone5_is1.dts                  | 8 ++++++++
 arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi        | 8 ++++++++
 arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi       | 8 ++++++++
 arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi     | 8 ++++++++
 arch/arm/dts/socfpga_cyclone5_sr1500.dts               | 8 ++++++++
 arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi  | 8 ++++++++
 11 files changed, 88 insertions(+)

diff --git a/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
index c44d1ee2fa..8aaec56285 100644
--- a/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
@@ -17,6 +17,14 @@
 	};
 };
 
+&rst {
+	u-boot,dm-pre-reloc;
+};
+
+&sdr {
+	u-boot,dm-pre-reloc;
+};
+
 &watchdog0 {
 	status = "disabled";
 };
diff --git a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
index a387071674..61907771e0 100644
--- a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
+++ b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
@@ -30,6 +30,14 @@
 	};
 };
 
+&rst {
+	u-boot,dm-pre-reloc;
+};
+
+&sdr {
+	u-boot,dm-pre-reloc;
+};
+
 &gmac1 {
 	status = "okay";
 	phy-mode = "rgmii";
diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi
index 08d81da169..00434185f6 100644
--- a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi
@@ -16,6 +16,14 @@
 	};
 };
 
+&rst {
+	u-boot,dm-pre-reloc;
+};
+
+&sdr {
+	u-boot,dm-pre-reloc;
+};
+
 &watchdog0 {
 	status = "disabled";
 };
diff --git a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
index e9105743ea..dc84f3de26 100644
--- a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
+++ b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
@@ -32,6 +32,14 @@
 	};
 };
 
+&rst {
+	u-boot,dm-pre-reloc;
+};
+
+&sdr {
+	u-boot,dm-pre-reloc;
+};
+
 &gmac1 {
 	status = "okay";
 	phy-mode = "rgmii";
diff --git a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
index 4f076bce93..585d914e30 100644
--- a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
+++ b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
@@ -30,6 +30,14 @@
 	};
 };
 
+&rst {
+	u-boot,dm-pre-reloc;
+};
+
+&sdr {
+	u-boot,dm-pre-reloc;
+};
+
 &gmac1 {
 	status = "okay";
 	phy-mode = "rgmii";
diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts
index b7054bfd5a..8947128be9 100644
--- a/arch/arm/dts/socfpga_cyclone5_is1.dts
+++ b/arch/arm/dts/socfpga_cyclone5_is1.dts
@@ -37,6 +37,14 @@
 	};
 };
 
+&rst {
+	u-boot,dm-pre-reloc;
+};
+
+&sdr {
+	u-boot,dm-pre-reloc;
+};
+
 &gmac1 {
 	status = "okay";
 	phy-mode = "rgmii";
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
index 9436e0fa8b..13d44072f4 100644
--- a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
@@ -17,6 +17,14 @@
 	};
 };
 
+&rst {
+	u-boot,dm-pre-reloc;
+};
+
+&sdr {
+	u-boot,dm-pre-reloc;
+};
+
 &can0 {
 	status = "okay";
 };
diff --git a/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi
index 648f1bd01d..07564a9f13 100644
--- a/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi
@@ -17,6 +17,14 @@
 	};
 };
 
+&rst {
+	u-boot,dm-pre-reloc;
+};
+
+&sdr {
+	u-boot,dm-pre-reloc;
+};
+
 &watchdog0 {
 	status = "disabled";
 };
diff --git a/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi
index 31bd1dba0f..cf0eb8bb8c 100644
--- a/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi
@@ -17,6 +17,14 @@
 	};
 };
 
+&rst {
+	u-boot,dm-pre-reloc;
+};
+
+&sdr {
+	u-boot,dm-pre-reloc;
+};
+
 &watchdog0 {
 	status = "disabled";
 };
diff --git a/arch/arm/dts/socfpga_cyclone5_sr1500.dts b/arch/arm/dts/socfpga_cyclone5_sr1500.dts
index 6a6c29be79..8a1678ed72 100644
--- a/arch/arm/dts/socfpga_cyclone5_sr1500.dts
+++ b/arch/arm/dts/socfpga_cyclone5_sr1500.dts
@@ -33,6 +33,14 @@
 	};
 };
 
+&rst {
+	u-boot,dm-pre-reloc;
+};
+
+&sdr {
+	u-boot,dm-pre-reloc;
+};
+
 &gmac1 {
 	status = "okay";
 	phy-mode = "rgmii";
diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
index 360b946ba2..90d1fd8858 100644
--- a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
@@ -17,6 +17,14 @@
 	};
 };
 
+&rst {
+	u-boot,dm-pre-reloc;
+};
+
+&sdr {
+	u-boot,dm-pre-reloc;
+};
+
 &watchdog0 {
 	status = "disabled";
 };
-- 
2.17.1