[PATCH v1] spi: cadence-qspi: Fix QSPI write issues

Chee Hong Ang chee.hong.ang at intel.com
Wed Aug 5 11:32:38 CEST 2020

QSPI driver perform chip select on every flash read/write
access. The driver need to disable/enable the QSPI controller
while performing chip select. This may cause some data lost
especially the QSPI controller is configured to run at slower
speed as it may take longer time to access the flash device.
This patch prevent the driver from disable/enable the QSPI
controller too soon and inadvertently halting any ongoing flash
read/write access by ensuring the QSPI controller is always in
idle mode after each read/write access.

Signed-off-by: Chee Hong Ang <chee.hong.ang at intel.com>
 drivers/spi/cadence_qspi_apb.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index f9675f7..5696eb3 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -648,6 +648,10 @@ cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
 	       plat->regbase + CQSPI_REG_INDIRECTRD);
+	/* Wait til QSPI is idle */
+	if (!cadence_qspi_wait_idle(plat->regbase))
+		return -EIO;
 	return 0;
@@ -763,6 +767,11 @@ cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
 	       plat->regbase + CQSPI_REG_INDIRECTWR);
 	if (bounce_buf)
+	/* Wait til QSPI is idle */
+	if (!cadence_qspi_wait_idle(plat->regbase))
+		return -EIO;
 	return 0;

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