[PATCH v1] spi: cadence-qspi: Fix QSPI write issues

Tan, Ley Foon ley.foon.tan at intel.com
Wed Aug 5 12:00:03 CEST 2020

> -----Original Message-----
> From: Ang, Chee Hong <chee.hong.ang at intel.com>
> Sent: Wednesday, August 5, 2020 5:33 PM
> To: u-boot at lists.denx.de
> Cc: Phil Edworthy <PHIL.EDWORTHY at renesas.com>; Vignesh R
> <vigneshr at ti.com>; Tom Rini <trini at konsulko.com>; See, Chin Liang
> <chin.liang.see at intel.com>; Tan, Ley Foon <ley.foon.tan at intel.com>; Ang,
> Chee Hong <chee.hong.ang at intel.com>; Chee, Tien Fong
> <tien.fong.chee at intel.com>; Lim, Elly Siew Chin
> <elly.siew.chin.lim at intel.com>
> Subject: [PATCH v1] spi: cadence-qspi: Fix QSPI write issues
> QSPI driver perform chip select on every flash read/write access. The driver
> need to disable/enable the QSPI controller while performing chip select. This
> may cause some data lost especially the QSPI controller is configured to run
> at slower speed as it may take longer time to access the flash device.
> This patch prevent the driver from disable/enable the QSPI controller too
> soon and inadvertently halting any ongoing flash read/write access by
> ensuring the QSPI controller is always in idle mode after each read/write
> access.
> Signed-off-by: Chee Hong Ang <chee.hong.ang at intel.com>
> ---
>  drivers/spi/cadence_qspi_apb.c | 9 +++++++++
>  1 file changed, 9 insertions(+)

Reviewed-by: Ley Foon Tan <ley.foon.tan at intel.com>

Ley Foon

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