Pull request: u-boot-riscv/master 20200825
uboot at andestech.com
uboot at andestech.com
Tue Aug 25 04:31:04 CEST 2020
Hi Tom,
Please pull some riscv updates:
- Sipeed Maix support S-mode.
- Provide command sbi.
- Use fdtdec_get_addr_size_auto_parent to get fu540 cache base address.
- Fix a compiler error with CONFIG_SPL_SMP=n.
- Fix sifive ram driver 32 compiler warnings.
- Fix kendryte/pll.h redefine nop() warning.
Thanks
Rick
https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/720564636
The following changes since commit 1aa3966173fe92fa3c46638ee8eb8b8491f521d6:
Merge tag 'u-boot-clk-24Aug2020' of https://gitlab.denx.de/u-boot/custodians/u-boot-clk (2020-08-24 09:06:02 -0400)
are available in the Git repository at:
git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to c92b50a44b95e706b9c0c97544bd7504fe6d36e9:
cmd: provide command sbi (2020-08-25 09:34:47 +0800)
----------------------------------------------------------------
Bin Meng (2):
riscv: fu540: Use correct API to get L2 cache controller base address
ram: sifive: Fix compiler warnings for 32-bit
Heinrich Schuchardt (4):
clk: kendryte/pll.h: do not redefine nop()
riscv: fix building with CONFIG_SPL_SMP=n
configs: defconfig for Sipeed Maix in S-mode
cmd: provide command sbi
arch/riscv/cpu/fu540/cache.c | 3 ++-
arch/riscv/include/asm/sbi.h | 2 ++
arch/riscv/lib/sbi.c | 36 ++++++++++++++++++++++++++++++++++++
arch/riscv/lib/spl.c | 2 +-
board/sipeed/maix/MAINTAINERS | 2 +-
cmd/Kconfig | 6 ++++++
cmd/riscv/Makefile | 1 +
cmd/riscv/sbi.c | 82 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
configs/sipeed_maix_smode_defconfig | 10 ++++++++++
doc/board/sipeed/maix.rst | 49 +++++++++++++++++++++++++++++++++++++++++++++++++
drivers/ram/sifive/fu540_ddr.c | 4 ++--
include/kendryte/pll.h | 5 +++++
12 files changed, 197 insertions(+), 5 deletions(-)
create mode 100644 cmd/riscv/sbi.c
create mode 100644 configs/sipeed_maix_smode_defconfig
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