[PATCH v2 5/7] arm: dts: k3-am69: ddr: Update to v0.12.0 of DDR config tool

[Francesco Dolcini]

Hello Neha, Kevin

On Mon, Nov 10, 2025 at 09:55:08AM +0530, Neha Malcom Francis wrote:
> On 07/11/25 21:14, Franz Schnyder wrote:
> > On Mon, Nov 03, 2025 at 12:40:33PM +0530, Neha Malcom Francis wrote:
> >> +#define DDRSS0_CTL_178_DATA 0x35000000
> >> +#define DDRSS0_CTL_186_DATA 0x00353500
> >> +#define DDRSS0_PI_275_DATA 0x00F30084
> >> +#define DDRSS0_PI_281_DATA 0x00F30084
> >> +#define DDRSS0_PI_287_DATA 0x00F30084
> >> +#define DDRSS0_PI_293_DATA 0x00F30084
> >> ....
> >> +#define DDRSS1_CTL_178_DATA 0x35000000
> >> +#define DDRSS1_CTL_186_DATA 0x00353500
> >> +#define DDRSS1_PI_275_DATA 0x00F30084
> >> +#define DDRSS1_PI_281_DATA 0x00F30084
> >> +#define DDRSS1_PI_287_DATA 0x00F30084
> >> +#define DDRSS1_PI_293_DATA 0x00F30084
> >> ....
> >> +#define DDRSS2_CTL_178_DATA 0x35000000
> >> +#define DDRSS2_CTL_186_DATA 0x00353500
> >> +#define DDRSS2_PI_275_DATA 0x00F30084
> >> +#define DDRSS2_PI_281_DATA 0x00F30084
> >> +#define DDRSS2_PI_287_DATA 0x00F30084
> >> +#define DDRSS2_PI_293_DATA 0x00F30084
> >> ....
> >> +#define DDRSS3_CTL_178_DATA 0x35350000
> >> +#define DDRSS3_CTL_186_DATA 0x00353535
> >> +#define DDRSS3_PI_275_DATA 0x35F30084
> >> +#define DDRSS3_PI_281_DATA 0x35F30084
> >> +#define DDRSS3_PI_287_DATA 0x35F30084
> >> +#define DDRSS3_PI_293_DATA 0x35F30084
> > 
> > When I compare the updated configuration to the one for our Aquila AM69
> > board, I can observe that you have set an on-die termination at boot
> > frequency only for DRAM3. DRAM, DRAM1 and DRAM2 do not seem to have any
> > termination enabled. Is this a mistake or is it intentional?
> 
> Kevin, could you explain the reasoning for this?

Any update on this?

Thanks
Francesco