[PATCH v1] drivers: clk: agilex5: Setting correct counter frequency in boot mode

[Chee, Tien Fong]

Hi Boon Khai,

> From: NG, BOON KHAI <boon.khai.ng at altera.com>
> Sent: Tuesday, April 14, 2026 3:43 PM
> To: U-boot Openlist <u-boot at lists.denx.de>; Chee, Tien Fong
> <tien.fong.chee at altera.com>
> Cc: Alice Guo <alice.guo at nxp.com>; YUSLAIMI, ALIF ZAKUAN
> <alif.zakuan.yuslaimi at altera.com>; Anshul Dalal <anshuld at ti.com>; Casey
> Connolly <casey.connolly at linaro.org>; Christian Marangi
> <ansuelsmth at gmail.com>; Ilias Apalodimas <ilias.apalodimas at linaro.org>; Neil
> Armstrong <neil.armstrong at linaro.org>; Quentin Schulz
> <quentin.schulz at cherry.de>; Rayagonda Kokatanur
> <rayagonda.kokatanur at broadcom.com>; Tien Fong Chee <tien.fong.chee at intel.com>;
> Tingting Meng <tingting.meng at altera.com>; Tom Rini <trini at konsulko.com>
> Subject: Re: [PATCH v1] drivers: clk: agilex5: Setting correct counter
> frequency in boot mode
> Re-add Tien Fong's Altera Email, with the patch's content.
> >
> >  
> > From: Tien Fong Chee <tien.fong.chee at intel.com>
> >
> > Counter frequency need to be set in 200Mhz when system in boot mode.
> > 400Mhz need to be set when system exit the boot mode with the PLL
> > generating the high frequency clock set by user.
> >
> > Signed-off-by: Tien Fong Chee <tien.fong.chee at intel.com>
> > Signed-off-by: Boon Khai Ng <boon.khai.ng at altera.com>
> > ---
> >  arch/arm/Kconfig | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > index 5508fce796a..4cc42ca393b 100644
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -30,6 +30,7 @@ config COUNTER_FREQUENCY
> >                          ROCKCHIP_RK3288 || ROCKCHIP_RK322X ||
> >                          ROCKCHIP_RK3036
> >          default 25000000 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A
> >          default 100000000 if ARCH_ZYNQMP
> > +       default 400000000 if ARCH_SOCFPGA && ARM64 &&
> > !TARGET_SOCFPGA_AGILEX5

The commit message describes a *runtime* transition (200MHz early, 400MHz
after PLL), but this patch only changes the Kconfig default (static).

All SoCFPGA64 counters are sourced from cs_at_clk and are 200MHz at early
boot, so defaulting COUNTER_FREQUENCY to 400MHz will break early
timeouts/delays.

Please respin:
- keep CONFIG_COUNTER_FREQUENCY default at 200000000 for SoCFPGA64, and
- perform the 400MHz update at runtime in the clock/PLL bring-up path,
  following the existing pattern in drivers/clk/altera/clk-agilex5.c
  (around the PLL setup section near line ~403), i.e. only update the
  counter frequency after the PLL is configured and the clock source has
  switched.
- Ensure correct namespace is used  CONFIG_ARCH_SOCFPGA_* .

Best regards,
Tien Fong