[U-Boot] [PATCH v2] nand: Fix cache and memory inconsistent issue

[Scott Wood]

On Fri, Nov 28, 2008 at 08:16:28PM +0800, Dave Liu wrote:
> +static void __flush_cache(ulong start, ulong size)

No gratuitous underscores.

> +{
> +	ulong addr, end;
> +	ulong cache_line = CONFIG_SYS_CACHELINE_SIZE;
> +
> +	end = start + size;
> +
> +	/* clean the dcache, make sure all of data to memory */
> +	for (addr = start; addr < end; addr += cache_line)
> +		asm ("dcbst 0,%0": :"r" (addr));

If (start % cache_line) > (end % cache_line), then you could miss
flushing the last cache line.

Make the asm volatile, with a memory clobber, and preferably with spaces
around the colons.

Please factor this out into arch code, and make it shareable with other
NAND code (such as nand_boot.c).

> +	/*
> +	 * We need clean dcache and invalidate
> +	 * to sync between icache and dcache
> +	 * before jump to RAM. make sure all of
> +	 * NAND data write to memory.

"Clean d-cache and invalidate i-cache, to make sure that
no stale data is executed."

-Scott