[U-Boot] [PATCH 3/5] SMDK5250: Creating a common file to be used by all variants of DDR
Hatim Ali
hatim.rv at samsung.com
Thu Feb 23 17:27:21 CET 2012
The patch creates a common file containing functions which will be
used by all variants of DDR.
Signed-off-by: Hatim Ali <hatim.rv at samsung.com>
diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile
index b18002a..3b4aa06 100644
--- a/board/samsung/smdk5250/Makefile
+++ b/board/samsung/smdk5250/Makefile
@@ -27,6 +27,7 @@ LIB = $(obj)lib$(BOARD).o
SOBJS := lowlevel_init.o
COBJS := clock_init.o
+COBJS += dmc_common.o
COBJS += dmc_init_lpddr2.o
COBJS += tzpc_init.o
diff --git a/board/samsung/smdk5250/dmc_common.c b/board/samsung/smdk5250/dmc_common.c
new file mode 100644
index 0000000..e940340
--- /dev/null
+++ b/board/samsung/smdk5250/dmc_common.c
@@ -0,0 +1,133 @@
+/*
+ * Mem setup common file for different types of DDR present on SMDK5250 boards.
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "setup.h"
+
+void config_zq(struct exynos5_phy_control *phy0_ctrl,
+ struct exynos5_phy_control *phy1_ctrl)
+{
+ unsigned long val = 0;
+ /*
+ * ZQ Calibration:
+ * Select Driver Strength,
+ * long calibration for manual calibration
+ */
+ val = PHY_CON16_RESET_VAL;
+ SET_ZQ_MODE_DDS_VAL(val);
+ SET_ZQ_MODE_TERM_VAL(val);
+ val |= ZQ_CLK_DIV_EN;
+ writel(val, &phy0_ctrl->phy_con16);
+ writel(val, &phy1_ctrl->phy_con16);
+
+ /* Disable termination */
+ val |= ZQ_MODE_NOTERM;
+ writel(val, &phy0_ctrl->phy_con16);
+ writel(val, &phy1_ctrl->phy_con16);
+
+ /* ZQ_MANUAL_START: Enable */
+ val |= ZQ_MANUAL_STR;
+ writel(val, &phy0_ctrl->phy_con16);
+ writel(val, &phy1_ctrl->phy_con16);
+ sdelay(0x10000);
+
+ /* ZQ_MANUAL_START: Disable */
+ val &= ~ZQ_MANUAL_STR;
+ writel(val, &phy0_ctrl->phy_con16);
+ writel(val, &phy1_ctrl->phy_con16);
+}
+
+void update_reset_dll(struct exynos5_dmc *dmc)
+{
+ unsigned long val;
+ /*
+ * Update DLL Information:
+ * Force DLL Resyncronization
+ */
+ val = readl(&dmc->phycontrol0);
+ val |= FP_RSYNC;
+ writel(val, &dmc->phycontrol0);
+
+ /* Reset Force DLL Resyncronization */
+ val = readl(&dmc->phycontrol0);
+ val &= ~FP_RSYNC;
+ writel(val, &dmc->phycontrol0);
+}
+
+void config_mrs(struct exynos5_dmc *dmc)
+{
+ unsigned long channel, chip, mask = 0, val;
+
+ for (channel = 0; channel < CONFIG_DMC_CHANNELS; channel++) {
+ SET_CMD_CHANNEL(mask, channel);
+ for (chip = 0; chip < CONFIG_CHIPS_PER_CHANNEL; chip++) {
+ SET_CMD_CHIP(mask, chip);
+
+ /* Sending NOP command */
+ val = DIRECT_CMD_NOP | mask;
+ writel(val, &dmc->directcmd);
+ sdelay(0x10000);
+
+ /* Sending EMRS/MRS commands */
+ val = DIRECT_CMD_MRS1 | mask;
+ writel(val, &dmc->directcmd);
+ sdelay(0x10000);
+
+ val = DIRECT_CMD_MRS2 | mask;
+ writel(val, &dmc->directcmd);
+ sdelay(0x10000);
+
+ val = DIRECT_CMD_MRS3 | mask;
+ writel(val, &dmc->directcmd);
+ sdelay(0x10000);
+
+ val = DIRECT_CMD_MRS4 | mask;
+ writel(val, &dmc->directcmd);
+ sdelay(0x10000);
+ }
+ }
+}
+
+void config_prech(struct exynos5_dmc *dmc)
+{
+ unsigned long channel, chip, mask = 0, val;
+
+ for (channel = 0; channel < CONFIG_DMC_CHANNELS; channel++) {
+ SET_CMD_CHANNEL(mask, channel);
+ for (chip = 0; chip < CONFIG_CHIPS_PER_CHANNEL; chip++) {
+ SET_CMD_CHIP(mask, chip);
+ /* PALL (all banks precharge) CMD */
+ val = DIRECT_CMD_PALL | mask;
+ writel(val, &dmc->directcmd);
+ sdelay(0x10000);
+ }
+ }
+}
+
+void config_memory(struct exynos5_dmc *dmc)
+{
+ writel(DMC_MEMCONFIG0_VAL, &dmc->memconfig0);
+ writel(DMC_MEMCONFIG1_VAL, &dmc->memconfig1);
+ writel(DMC_MEMBASECONFIG0_VAL, &dmc->membaseconfig0);
+ writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1);
+}
diff --git a/board/samsung/smdk5250/dmc_init_lpddr2.c b/board/samsung/smdk5250/dmc_init_lpddr2.c
index 846469e..9b07f21 100644
--- a/board/samsung/smdk5250/dmc_init_lpddr2.c
+++ b/board/samsung/smdk5250/dmc_init_lpddr2.c
@@ -1,5 +1,5 @@
/*
- * Memory setup for SMDK5250 board based on EXYNOS5
+ * LPDDR2 mem setup file for SMDK5250 board based on EXYNOS5
*
* Copyright (C) 2012 Samsung Electronics
*
@@ -30,24 +30,8 @@
#include "setup.h"
/* APLL : 1GHz */
-/* MCLK_CDREX: MCLK_CDREX_533*/
-/* LPDDR support: LPDDR2 */
-static void reset_phy_ctrl(void);
-static void config_zq(struct exynos5_phy_control *,
- struct exynos5_phy_control *);
-static void update_reset_dll(struct exynos5_dmc *);
-static void config_cdrex(void);
-static void config_mrs(struct exynos5_dmc *);
-static void sec_sdram_phy_init(struct exynos5_dmc *);
-static void config_prech(struct exynos5_dmc *);
-static void config_rdlvl(struct exynos5_dmc *,
- struct exynos5_phy_control *,
- struct exynos5_phy_control *);
-static void config_memory(struct exynos5_dmc *);
-
-static void config_offsets(unsigned int,
- struct exynos5_phy_control *,
- struct exynos5_phy_control *);
+/* MCLK_CDREX: 533Mhz */
+/* Memory Type: LPDDR2 */
static void reset_phy_ctrl(void)
{
@@ -57,109 +41,6 @@ static void reset_phy_ctrl(void)
sdelay(0x10000);
}
-static void config_zq(struct exynos5_phy_control *phy0_ctrl,
- struct exynos5_phy_control *phy1_ctrl)
-{
- unsigned long val = 0;
- /*
- * ZQ Calibration:
- * Select Driver Strength,
- * long calibration for manual calibration
- */
- val = PHY_CON16_RESET_VAL;
- SET_ZQ_MODE_DDS_VAL(val);
- SET_ZQ_MODE_TERM_VAL(val);
- val |= ZQ_CLK_DIV_EN;
- writel(val, &phy0_ctrl->phy_con16);
- writel(val, &phy1_ctrl->phy_con16);
-
- /* Disable termination */
- val |= ZQ_MODE_NOTERM;
- writel(val, &phy0_ctrl->phy_con16);
- writel(val, &phy1_ctrl->phy_con16);
-
- /* ZQ_MANUAL_START: Enable */
- val |= ZQ_MANUAL_STR;
- writel(val, &phy0_ctrl->phy_con16);
- writel(val, &phy1_ctrl->phy_con16);
- sdelay(0x10000);
-
- /* ZQ_MANUAL_START: Disable */
- val &= ~ZQ_MANUAL_STR;
- writel(val, &phy0_ctrl->phy_con16);
- writel(val, &phy1_ctrl->phy_con16);
-}
-
-static void update_reset_dll(struct exynos5_dmc *dmc)
-{
- unsigned long val;
- /*
- * Update DLL Information:
- * Force DLL Resyncronization
- */
- val = readl(&dmc->phycontrol0);
- val |= FP_RSYNC;
- writel(val, &dmc->phycontrol0);
-
- /* Reset Force DLL Resyncronization */
- val = readl(&dmc->phycontrol0);
- val &= ~FP_RSYNC;
- writel(val, &dmc->phycontrol0);
-}
-
-static void config_mrs(struct exynos5_dmc *dmc)
-{
- unsigned long channel, chip, mask = 0, val;
-
- for (channel = 0; channel < CONFIG_DMC_CHANNELS; channel++) {
- SET_CMD_CHANNEL(mask, channel);
- for (chip = 0; chip < CONFIG_CHIPS_PER_CHANNEL; chip++) {
- /*
- * NOP CMD:
- * Assert and hold CKE to logic high level
- */
- SET_CMD_CHIP(mask, chip);
- val = DIRECT_CMD_NOP | mask;
- writel(val, &dmc->directcmd);
- sdelay(0x10000);
-
- /* EMRS, MRS Cmds(Mode Reg Settings) Using Direct Cmd */
- val = DIRECT_CMD_MRS1 | mask;
- writel(val, &dmc->directcmd);
- sdelay(0x10000);
-
- val = DIRECT_CMD_MRS2 | mask;
- writel(val, &dmc->directcmd);
- sdelay(0x10000);
-
- /* MCLK_CDREX_533 */
- val = DIRECT_CMD_MRS3 | mask;
- writel(val, &dmc->directcmd);
- sdelay(0x10000);
-
- val = DIRECT_CMD_MRS4 | mask;
- writel(val, &dmc->directcmd);
- sdelay(0x10000);
- }
- }
-}
-
-static void config_prech(struct exynos5_dmc *dmc)
-{
- unsigned long channel, chip, mask = 0, val;
-
- for (channel = 0; channel < CONFIG_DMC_CHANNELS; channel++) {
- SET_CMD_CHANNEL(mask, channel);
- for (chip = 0; chip < CONFIG_CHIPS_PER_CHANNEL; chip++) {
- SET_CMD_CHIP(mask, chip);
- /* PALL (all banks precharge) CMD */
- val = DIRECT_CMD_PALL | mask;
- writel(val, &dmc->directcmd);
- sdelay(0x10000);
- }
- }
-}
-
static void sec_sdram_phy_init(struct exynos5_dmc *dmc)
{
unsigned long val;
@@ -305,41 +186,6 @@ static void config_rdlvl(struct exynos5_dmc *dmc,
}
#endif
-static void config_memory(struct exynos5_dmc *dmc)
-{
- /*
- * Memory Configuration Chip 0
- * Address Mapping: Interleaved
- * Number of Column address Bits: 10 bits
- * Number of Rows Address Bits: 14
- * Number of Banks: 8
- */
- writel(DMC_MEMCONFIG0_VAL, &dmc->memconfig0);
-
- /*
- * Memory Configuration Chip 1
- * Address Mapping: Interleaved
- * Number of Column address Bits: 10 bits
- * Number of Rows Address Bits: 14
- * Number of Banks: 8
- */
- writel(DMC_MEMCONFIG1_VAL, &dmc->memconfig1);
-
- /*
- * Chip0: AXI
- * AXI Base Address: 0x40000000
- * AXI Base Address Mask: 0x780
- */
- writel(DMC_MEMBASECONFIG0_VAL, &dmc->membaseconfig0);
-
- /*
- * Chip1: AXI
- * AXI Base Address: 0x80000000
- * AXI Base Address Mask: 0x780
- */
- writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1);
-}
-
void mem_ctrl_init()
{
struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
diff --git a/board/samsung/smdk5250/setup.h b/board/samsung/smdk5250/setup.h
index cf572ac..c061440 100644
--- a/board/samsung/smdk5250/setup.h
+++ b/board/samsung/smdk5250/setup.h
@@ -28,6 +28,7 @@
#include <config.h>
#include <version.h>
#include <asm/arch/cpu.h>
+#include <asm/arch/dmc.h>
/* GPIO Offsets for UART: GPIO Contol Register */
#define EXYNOS5_GPIO_A0_CON_OFFSET 0x0
@@ -448,5 +449,10 @@ void sdelay(unsigned long);
void mem_ctrl_init(void);
void system_clock_init(void);
void tzpc_init(void);
+void config_zq(struct exynos5_phy_control *, struct exynos5_phy_control *);
+void update_reset_dll(struct exynos5_dmc *);
+void config_mrs(struct exynos5_dmc *);
+void config_prech(struct exynos5_dmc *);
+void config_memory(struct exynos5_dmc *);
#endif
--
1.7.2.3
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