[U-Boot] [PATCH v2] mx35 iomux: correct offsets of IOMUX registers
Philip Paeps
philip at paeps.cx
Wed Apr 10 00:44:31 CEST 2013
This makes mxc_iomux_set_input() work correctly. Previously, the
incorrect offset of IOMUXSW_INPUT_CTL caused mxc_iomux_set_input()
to write to the wrong register, possibly resulting in unexpected
behaviour.
Signed-off-by: Philip Paeps <philip at paeps.cx>
---
Changes in v2:
- While here, also correct the offset of the last pad control
register. This is mostly cosmetic.
arch/arm/cpu/arm1136/mx35/iomux.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/arm1136/mx35/iomux.c b/arch/arm/cpu/arm1136/mx35/iomux.c
index a302575..698909e 100644
--- a/arch/arm/cpu/arm1136/mx35/iomux.c
+++ b/arch/arm/cpu/arm1136/mx35/iomux.c
@@ -34,8 +34,8 @@ enum iomux_reg_addr {
IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR + 4, /* MUX control */
IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + 0x324, /* last MUX control */
IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + 0x328, /* Pad control */
- IOMUXSW_PAD_END = IOMUXC_BASE_ADDR + 0x794, /* last Pad control */
- IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + 0x7AC, /* input select */
+ IOMUXSW_PAD_END = IOMUXC_BASE_ADDR + 0x7A4, /* last Pad control */
+ IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + 0x7A8, /* input select */
IOMUXSW_INPUT_END = IOMUXC_BASE_ADDR + 0x9F4, /* last input select */
};
--
1.7.2.5
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